f0d21f090e
In order to be able to provide 48MHz on PLL-Q, slightly decrease core clock freq. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org> |
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.. | ||
doc | ||
support | ||
arduino_r3_connector.dtsi | ||
board.cmake | ||
Kconfig.board | ||
Kconfig.defconfig | ||
stm32f469i_disco.dts | ||
stm32f469i_disco.yaml | ||
stm32f469i_disco_defconfig |