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zephyr/drivers/clock_control/clock_stm32_ll_h7.c

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drivers/clock_control: STM32H7 support Provide basic clock control driver for STM32H7. Bus clock activation is done through CM7 and CM4 common registers so we don't have to care to the CPU Id before accessing. Accesses are not protected for now. Only possible configuration is system clock source set to HSE driven PLL. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2019-07-01 14:12:48 +02:00
/*
*
* Copyright (c) 2019 Linaro Limited.
drivers: clock_control: stm32h7: Add HSE,HSI,CSI,PLL sysclk opt. Add HSE,HSI,CSI,PLL as system clock options. Also add correct configuration of the PLL. New sysclk options: - HSI with: CONFIG_CLOCK_STM32_SYSCLK_SRC_HSI=y - HSE with: CONFIG_CLOCK_STM32_SYSCLK_SRC_HSE=y - CSI with: CONFIG_CLOCK_STM32_SYSCLK_SRC_CSI=y Existing sysclk options: - PLL with: CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y PLL clock options: - More PLL source clocks: Existing: 1. HSE with: CONFIG_CLOCK_STM32_PLL_SRC_HSE=y New: 2. HSI with: CONFIG_CLOCK_STM32_PLL_SRC_HSI=y 3. CSI with: CONFIG_CLOCK_STM32_PLL_SRC_CSI=y - PLL vco input range is auto-calculated based on PLL DIVM1 -> Example for sysclock 96MHz generated with PLL from HSI CONFIG_CLOCK_STM32_PLL_SRC_HSI=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=96000000 CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y CONFIG_CLOCK_STM32_PLL_M_DIVISOR=4 CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=12 CONFIG_CLOCK_STM32_PLL_P_DIVISOR=2 CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=4 CONFIG_CLOCK_STM32_PLL_R_DIVISOR=2 Use LL_SetFlashLatency function from stm32h7xx_ll_utils.h instead to setup the correct latency. Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
2020-07-09 21:42:46 +02:00
* Copyright (c) 2020 Jeremy LOCHE
drivers/clock_control: STM32H7 support Provide basic clock control driver for STM32H7. Bus clock activation is done through CM7 and CM4 common registers so we don't have to care to the CPU Id before accessing. Accesses are not protected for now. Only possible configuration is system clock source set to HSE driven PLL. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2019-07-01 14:12:48 +02:00
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <soc.h>
drivers: clock_control: stm32: use generic LL headers Use generic LL headers instead of depending on soc.h. Signed-off-by: Martin Jäger <martin@libre.solar>
2020-11-20 20:28:06 +01:00
#include <stm32_ll_bus.h>
#include <stm32_ll_pwr.h>
#include <stm32_ll_rcc.h>
#include <stm32_ll_utils.h>
treewide: use full path to clock_control.h header The build infrastructure should not be adding the drivers subdirectory to the include path. Fix the legacy uses that depended on that addition. Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
2020-01-25 12:34:53 +01:00
#include <drivers/clock_control.h>
include: Fix use of <misc/FOO.h> -> <sys/FOO.h> Fix #include <misc/FOO.h> as misc/FOO.h has been deprecated and should be #include <sys/FOO.h>. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-12-09 18:18:21 +01:00
#include <sys/util.h>
treewide: use full path to clock_control/stm32_clock_control.h header The build infrastructure should not be adding the drivers subdirectory to the include path. Fix the legacy uses that depended on that addition. Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
2020-01-25 12:34:53 +01:00
#include <drivers/clock_control/stm32_clock_control.h>
drivers: STM32 dualcore concurrent register access protection with HSEM In case of dualcore, STM32H7, STM32W and STM32MP1, protect concurrent register write access with HSEM. Done for following drivers: clock_control, counter, flash, gpio, interrupt_controller Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
2020-06-23 09:48:07 +02:00
#include "stm32_hsem.h"
drivers/clock_control: STM32H7 support Provide basic clock control driver for STM32H7. Bus clock activation is done through CM7 and CM4 common registers so we don't have to care to the CPU Id before accessing. Accesses are not protected for now. Only possible configuration is system clock source set to HSE driven PLL. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2019-07-01 14:12:48 +02:00
/* Macros to fill up prescaler values */
drivers: clock_control: stm32h7 add HSI divisor support Add HSI divisor support for clock tree configuration. Removed HSI calibration trimming to comply with common STM32 implementation and use reset default configuration instead. Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
2020-07-30 09:45:32 +02:00
#define z_hsi_divider(v) LL_RCC_HSI_DIV ## v
#define hsi_divider(v) z_hsi_divider(v)
drivers/clock_control: STM32H7 support Provide basic clock control driver for STM32H7. Bus clock activation is done through CM7 and CM4 common registers so we don't have to care to the CPU Id before accessing. Accesses are not protected for now. Only possible configuration is system clock source set to HSE driven PLL. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2019-07-01 14:12:48 +02:00
#define z_sysclk_prescaler(v) LL_RCC_SYSCLK_DIV_ ## v
#define sysclk_prescaler(v) z_sysclk_prescaler(v)
#define z_ahb_prescaler(v) LL_RCC_AHB_DIV_ ## v
#define ahb_prescaler(v) z_ahb_prescaler(v)
#define z_apb1_prescaler(v) LL_RCC_APB1_DIV_ ## v
#define apb1_prescaler(v) z_apb1_prescaler(v)
#define z_apb2_prescaler(v) LL_RCC_APB2_DIV_ ## v
#define apb2_prescaler(v) z_apb2_prescaler(v)
#define z_apb3_prescaler(v) LL_RCC_APB3_DIV_ ## v
#define apb3_prescaler(v) z_apb3_prescaler(v)
#define z_apb4_prescaler(v) LL_RCC_APB4_DIV_ ## v
#define apb4_prescaler(v) z_apb4_prescaler(v)
drivers: clock_control: stm32h7 add preprocessor clock check Adds preprocessor clock feasibility check to avoid setting too high clocks to SYSCLK,AHB,APBx buses. Also checks if CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC matches with the desired clock configuration by the M7 core. Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
2020-07-29 14:41:20 +02:00
/* Macro to check for clock feasability */
/* It is Cortex M7's responsibility to setup clock tree */
/* This check should only be performed for the M7 core code */
#ifdef CONFIG_CPU_CORTEX_M7
/* Define primary oscillator frequencies */
/* Suppress the cast to uint32_t which */
/* prevents from compare with #if > operator*/
/* original defines in stm32h7xx_hal_conf.h*/
#define HSI_FREQ 64000000UL /* HSI_VALUE ((uint32_t)64000000) */
/* HSE_VALUE overridden by the build system without C cast to uint*/
/* Build system doesn't provide the UL type suffix for HSE_VALUE */
/* Force HSE_FREQ to be cast to preprocessor UL to prevent overflow*/
/* Only use these constants in preprocessor expressions */
#define HSE_FREQ HSE_VALUE
#define CSI_FREQ 4000000UL /* CSI_VALUE ((uint32_t)4000000) */
/* Choose PLL SRC */
drivers: clock_control: stm32h7: Use dts based configuration macros Update stm32h7 clock_control driver to make use of macros allowing dts based configuration in coexistance with existing Kconfig method. Note: Use of IS_ENABLED is removed as it generates warnings in checkpatch. This checkpatch behavior needs to be reviewed but may first require a little clean up of IS_ENABLED macro. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-04-29 14:41:58 +02:00
#if STM32_PLL_SRC_HSI
#define PLLSRC_FREQ ((HSI_FREQ)/(STM32_HSI_DIVISOR))
#elif STM32_PLL_SRC_CSI
drivers: clock_control: stm32h7 add preprocessor clock check Adds preprocessor clock feasibility check to avoid setting too high clocks to SYSCLK,AHB,APBx buses. Also checks if CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC matches with the desired clock configuration by the M7 core. Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
2020-07-29 14:41:20 +02:00
#define PLLSRC_FREQ CSI_FREQ
drivers: clock_control: stm32h7: Use dts based configuration macros Update stm32h7 clock_control driver to make use of macros allowing dts based configuration in coexistance with existing Kconfig method. Note: Use of IS_ENABLED is removed as it generates warnings in checkpatch. This checkpatch behavior needs to be reviewed but may first require a little clean up of IS_ENABLED macro. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-04-29 14:41:58 +02:00
#elif STM32_PLL_SRC_HSE
drivers: clock_control: stm32h7 add preprocessor clock check Adds preprocessor clock feasibility check to avoid setting too high clocks to SYSCLK,AHB,APBx buses. Also checks if CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC matches with the desired clock configuration by the M7 core. Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
2020-07-29 14:41:20 +02:00
#define PLLSRC_FREQ HSE_FREQ
#else
#define PLLSRC_FREQ 0
#endif
/* Given source clock and dividers, computed the output frequency of PLLP */
#define PLLP_FREQ(pllsrc_freq, divm, divn, divp) (((pllsrc_freq)*\
(divn))/((divm)*(divp)))
/* PLL P output frequency value */
#define PLLP_VALUE PLLP_FREQ(\
PLLSRC_FREQ,\
drivers: clock_control: stm32h7: Use dts based configuration macros Update stm32h7 clock_control driver to make use of macros allowing dts based configuration in coexistance with existing Kconfig method. Note: Use of IS_ENABLED is removed as it generates warnings in checkpatch. This checkpatch behavior needs to be reviewed but may first require a little clean up of IS_ENABLED macro. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-04-29 14:41:58 +02:00
STM32_PLL_M_DIVISOR,\
STM32_PLL_N_MULTIPLIER,\
STM32_PLL_P_DIVISOR)
drivers: clock_control: stm32h7 add preprocessor clock check Adds preprocessor clock feasibility check to avoid setting too high clocks to SYSCLK,AHB,APBx buses. Also checks if CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC matches with the desired clock configuration by the M7 core. Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
2020-07-29 14:41:20 +02:00
/* SYSCLKSRC before the D1CPRE prescaler */
drivers: clock_control: stm32h7: Use dts based configuration macros Update stm32h7 clock_control driver to make use of macros allowing dts based configuration in coexistance with existing Kconfig method. Note: Use of IS_ENABLED is removed as it generates warnings in checkpatch. This checkpatch behavior needs to be reviewed but may first require a little clean up of IS_ENABLED macro. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-04-29 14:41:58 +02:00
#if STM32_SYSCLK_SRC_PLL
drivers: clock_control: stm32h7 add preprocessor clock check Adds preprocessor clock feasibility check to avoid setting too high clocks to SYSCLK,AHB,APBx buses. Also checks if CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC matches with the desired clock configuration by the M7 core. Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
2020-07-29 14:41:20 +02:00
#define SYSCLKSRC_FREQ PLLP_VALUE
drivers: clock_control: stm32h7: Use dts based configuration macros Update stm32h7 clock_control driver to make use of macros allowing dts based configuration in coexistance with existing Kconfig method. Note: Use of IS_ENABLED is removed as it generates warnings in checkpatch. This checkpatch behavior needs to be reviewed but may first require a little clean up of IS_ENABLED macro. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-04-29 14:41:58 +02:00
#elif STM32_SYSCLK_SRC_HSI
#define SYSCLKSRC_FREQ ((HSI_FREQ)/(STM32_HSI_DIVISOR))
#elif STM32_SYSCLK_SRC_CSI
drivers: clock_control: stm32h7 add preprocessor clock check Adds preprocessor clock feasibility check to avoid setting too high clocks to SYSCLK,AHB,APBx buses. Also checks if CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC matches with the desired clock configuration by the M7 core. Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
2020-07-29 14:41:20 +02:00
#define SYSCLKSRC_FREQ CSI_FREQ
drivers: clock_control: stm32h7: Use dts based configuration macros Update stm32h7 clock_control driver to make use of macros allowing dts based configuration in coexistance with existing Kconfig method. Note: Use of IS_ENABLED is removed as it generates warnings in checkpatch. This checkpatch behavior needs to be reviewed but may first require a little clean up of IS_ENABLED macro. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-04-29 14:41:58 +02:00
#elif STM32_SYSCLK_SRC_HSE
drivers: clock_control: stm32h7 add preprocessor clock check Adds preprocessor clock feasibility check to avoid setting too high clocks to SYSCLK,AHB,APBx buses. Also checks if CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC matches with the desired clock configuration by the M7 core. Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
2020-07-29 14:41:20 +02:00
#define SYSCLKSRC_FREQ HSE_FREQ
#endif
/* ARM Sys CPU Clock before HPRE prescaler */
drivers: clock_control: stm32h7: Use dts based configuration macros Update stm32h7 clock_control driver to make use of macros allowing dts based configuration in coexistance with existing Kconfig method. Note: Use of IS_ENABLED is removed as it generates warnings in checkpatch. This checkpatch behavior needs to be reviewed but may first require a little clean up of IS_ENABLED macro. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-04-29 14:41:58 +02:00
#define SYSCLK_FREQ ((SYSCLKSRC_FREQ)/(STM32_D1CPRE))
#define AHB_FREQ ((SYSCLK_FREQ)/(STM32_HPRE))
#define APB1_FREQ ((AHB_FREQ)/(STM32_D2PPRE1))
#define APB2_FREQ ((AHB_FREQ)/(STM32_D2PPRE2))
#define APB3_FREQ ((AHB_FREQ)/(STM32_D1PPRE))
#define APB4_FREQ ((AHB_FREQ)/(STM32_D3PPRE))
drivers: clock_control: stm32h7 add preprocessor clock check Adds preprocessor clock feasibility check to avoid setting too high clocks to SYSCLK,AHB,APBx buses. Also checks if CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC matches with the desired clock configuration by the M7 core. Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
2020-07-29 14:41:20 +02:00
/* Datasheet maximum frequency definitions */
drivers: clock_control: stm32h7 increase max clock values according to stm32h723 Signed-off-by: Alexander Kozhinov <AlexanderKozhinov@yandex.com>
2020-10-31 22:57:56 +01:00
#if defined(CONFIG_SOC_STM32H743XX) ||\
drivers: clock_control: Add support for STM32H753XX. Added support for STM32H753XX by adding CONFIG_SOC_STM32H753XX to list of H7 SoC with maximum 480MHz SYSCLK. Signed-off-by: Jeremy Wood <jeremy@bcdevices.com>
2021-03-15 18:20:36 +01:00
defined(CONFIG_SOC_STM32H745XX) ||\
defined(CONFIG_SOC_STM32H747XX) ||\
defined(CONFIG_SOC_STM32H750XX) ||\
defined(CONFIG_SOC_STM32H753XX)
drivers: clock_control: stm32h7 increase max clock values according to stm32h723 Signed-off-by: Alexander Kozhinov <AlexanderKozhinov@yandex.com>
2020-10-31 22:57:56 +01:00
/* All h7 SoC with maximum 480MHz SYSCLK */
#define SYSCLK_FREQ_MAX 480000000UL
#define AHB_FREQ_MAX 240000000UL
#define APBx_FREQ_MAX 120000000UL
boards: arm: add STM32H735G discovery kit Add the STM32H735G discovery kit to the available boards. Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
2021-06-29 14:15:50 +02:00
#elif defined(CONFIG_SOC_STM32H723XX) ||\
defined(CONFIG_SOC_STM32H735XX)
drivers: clock_control: stm32h7 increase max clock values according to stm32h723 Signed-off-by: Alexander Kozhinov <AlexanderKozhinov@yandex.com>
2020-10-31 22:57:56 +01:00
/* All h7 SoC with maximum 550MHz SYSCLK */
#define SYSCLK_FREQ_MAX 550000000UL
#define AHB_FREQ_MAX 275000000UL
#define APBx_FREQ_MAX 137500000UL
#else
/* Default: All h7 SoC with maximum 280MHz SYSCLK */
#define SYSCLK_FREQ_MAX 280000000UL
#define AHB_FREQ_MAX 140000000UL
#define APBx_FREQ_MAX 70000000UL
#endif
drivers: clock_control: stm32h7 add preprocessor clock check Adds preprocessor clock feasibility check to avoid setting too high clocks to SYSCLK,AHB,APBx buses. Also checks if CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC matches with the desired clock configuration by the M7 core. Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
2020-07-29 14:41:20 +02:00
#if SYSCLK_FREQ > SYSCLK_FREQ_MAX
drivers: clock_control: stm32h7 increase max clock values according to stm32h723 Signed-off-by: Alexander Kozhinov <AlexanderKozhinov@yandex.com>
2020-10-31 22:57:56 +01:00
#error "SYSCLK frequency is too high!"
drivers: clock_control: stm32h7 add preprocessor clock check Adds preprocessor clock feasibility check to avoid setting too high clocks to SYSCLK,AHB,APBx buses. Also checks if CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC matches with the desired clock configuration by the M7 core. Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
2020-07-29 14:41:20 +02:00
#endif
#if AHB_FREQ > AHB_FREQ_MAX
drivers: clock_control: stm32h7 increase max clock values according to stm32h723 Signed-off-by: Alexander Kozhinov <AlexanderKozhinov@yandex.com>
2020-10-31 22:57:56 +01:00
#error "AHB frequency is too high!"
drivers: clock_control: stm32h7 add preprocessor clock check Adds preprocessor clock feasibility check to avoid setting too high clocks to SYSCLK,AHB,APBx buses. Also checks if CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC matches with the desired clock configuration by the M7 core. Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
2020-07-29 14:41:20 +02:00
#endif
#if APB1_FREQ > APBx_FREQ_MAX
drivers: clock_control: stm32h7 increase max clock values according to stm32h723 Signed-off-by: Alexander Kozhinov <AlexanderKozhinov@yandex.com>
2020-10-31 22:57:56 +01:00
#error "APB1 frequency is too high!"
drivers: clock_control: stm32h7 add preprocessor clock check Adds preprocessor clock feasibility check to avoid setting too high clocks to SYSCLK,AHB,APBx buses. Also checks if CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC matches with the desired clock configuration by the M7 core. Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
2020-07-29 14:41:20 +02:00
#endif
#if APB2_FREQ > APBx_FREQ_MAX
drivers: clock_control: stm32h7 increase max clock values according to stm32h723 Signed-off-by: Alexander Kozhinov <AlexanderKozhinov@yandex.com>
2020-10-31 22:57:56 +01:00
#error "APB2 frequency is too high!"
drivers: clock_control: stm32h7 add preprocessor clock check Adds preprocessor clock feasibility check to avoid setting too high clocks to SYSCLK,AHB,APBx buses. Also checks if CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC matches with the desired clock configuration by the M7 core. Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
2020-07-29 14:41:20 +02:00
#endif
#if APB3_FREQ > APBx_FREQ_MAX
drivers: clock_control: stm32h7 increase max clock values according to stm32h723 Signed-off-by: Alexander Kozhinov <AlexanderKozhinov@yandex.com>
2020-10-31 22:57:56 +01:00
#error "APB3 frequency is too high!"
drivers: clock_control: stm32h7 add preprocessor clock check Adds preprocessor clock feasibility check to avoid setting too high clocks to SYSCLK,AHB,APBx buses. Also checks if CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC matches with the desired clock configuration by the M7 core. Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
2020-07-29 14:41:20 +02:00
#endif
#if APB4_FREQ > APBx_FREQ_MAX
drivers: clock_control: stm32h7 increase max clock values according to stm32h723 Signed-off-by: Alexander Kozhinov <AlexanderKozhinov@yandex.com>
2020-10-31 22:57:56 +01:00
#error "APB4 frequency is too high!"
drivers: clock_control: stm32h7 add preprocessor clock check Adds preprocessor clock feasibility check to avoid setting too high clocks to SYSCLK,AHB,APBx buses. Also checks if CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC matches with the desired clock configuration by the M7 core. Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
2020-07-29 14:41:20 +02:00
#endif
#if SYSCLK_FREQ != CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC
drivers/clock_control: stm32h7: Fix line break on #error Line break on #error directive is confusing github and ending up breaking syntax highligthing in github UI which makes me nervous during review. Convert error message to a one liner. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-01-08 17:34:19 +01:00
#error "SYS clock frequency for M7 core doesn't match CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC"
drivers: clock_control: stm32h7 add preprocessor clock check Adds preprocessor clock feasibility check to avoid setting too high clocks to SYSCLK,AHB,APBx buses. Also checks if CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC matches with the desired clock configuration by the M7 core. Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
2020-07-29 14:41:20 +02:00
#endif
/* end of clock feasability check */
#endif /* CONFIG_CPU_CORTEX_M7 */
stm32: clock_control: Enforce HCLK prescaler value STM32 clock control subsystem allows to configure a different frequency value for core clock (SYSCLK) and AHB clock (HCLK). Though, it is HCLK which is used to feed Cortex Systick timer which is used in zephyr as reference system clock. If HCLK frequency is configured to a different value from SYSCLK frequency, whole system is exposed to desynchro between zephyr clock subsytem and STM32 HW configuration. To prevent this, and until zephyr clock subsystem is changed to be aware of this potential configuration, enforce AHB prescaler value to 1 (which is current default value in use for all STM32 based boards). On STM32H7, enforce D1CPRE which fills the same role as ABH precaler. On STM32MP1, the equivalent setting is done on A7 core, so it is not exposed to the same issue as long as SYS_CLOCK_HW_CYCLES_PER_SEC is set with the 'mlhclk_ck' clock frequency value. Update matching boards documentation. Fixes #17188 Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2019-08-02 09:28:29 +02:00
#if defined(CONFIG_CPU_CORTEX_M7)
drivers: clock_control: stm32h7: Use dts based configuration macros Update stm32h7 clock_control driver to make use of macros allowing dts based configuration in coexistance with existing Kconfig method. Note: Use of IS_ENABLED is removed as it generates warnings in checkpatch. This checkpatch behavior needs to be reviewed but may first require a little clean up of IS_ENABLED macro. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-04-29 14:41:58 +02:00
#if STM32_D1CPRE > 1
stm32: clock_control: Enforce HCLK prescaler value STM32 clock control subsystem allows to configure a different frequency value for core clock (SYSCLK) and AHB clock (HCLK). Though, it is HCLK which is used to feed Cortex Systick timer which is used in zephyr as reference system clock. If HCLK frequency is configured to a different value from SYSCLK frequency, whole system is exposed to desynchro between zephyr clock subsytem and STM32 HW configuration. To prevent this, and until zephyr clock subsystem is changed to be aware of this potential configuration, enforce AHB prescaler value to 1 (which is current default value in use for all STM32 based boards). On STM32H7, enforce D1CPRE which fills the same role as ABH precaler. On STM32MP1, the equivalent setting is done on A7 core, so it is not exposed to the same issue as long as SYS_CLOCK_HW_CYCLES_PER_SEC is set with the 'mlhclk_ck' clock frequency value. Update matching boards documentation. Fixes #17188 Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2019-08-02 09:28:29 +02:00
/*
* D1CPRE prescaler allows to set a HCLK frequency lower than SYSCLK frequency.
* Though, zephyr doesn't make a difference today between these two clocks.
* So, changing this prescaler is not allowed until it is made possible to
* use them independently in zephyr clock subsystem.
*/
#error "D1CPRE presacler can't be higher than 1"
#endif
#endif /* CONFIG_CPU_CORTEX_M7 */
zephyr: replace zephyr integer types with C99 types git grep -l 'u\(8\|16\|32\|64\)_t' | \ xargs sed -i "s/u\(8\|16\|32\|64\)_t/uint\1_t/g" git grep -l 's\(8\|16\|32\|64\)_t' | \ xargs sed -i "s/s\(8\|16\|32\|64\)_t/int\1_t/g" Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-05-27 18:26:57 +02:00
static uint32_t get_bus_clock(uint32_t clock, uint32_t prescaler)
drivers/clock_control: STM32H7 support Provide basic clock control driver for STM32H7. Bus clock activation is done through CM7 and CM4 common registers so we don't have to care to the CPU Id before accessing. Accesses are not protected for now. Only possible configuration is system clock source set to HSE driven PLL. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2019-07-01 14:12:48 +02:00
{
return clock / prescaler;
}
drivers: clock_control: stm32h7: Add HSE,HSI,CSI,PLL sysclk opt. Add HSE,HSI,CSI,PLL as system clock options. Also add correct configuration of the PLL. New sysclk options: - HSI with: CONFIG_CLOCK_STM32_SYSCLK_SRC_HSI=y - HSE with: CONFIG_CLOCK_STM32_SYSCLK_SRC_HSE=y - CSI with: CONFIG_CLOCK_STM32_SYSCLK_SRC_CSI=y Existing sysclk options: - PLL with: CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y PLL clock options: - More PLL source clocks: Existing: 1. HSE with: CONFIG_CLOCK_STM32_PLL_SRC_HSE=y New: 2. HSI with: CONFIG_CLOCK_STM32_PLL_SRC_HSI=y 3. CSI with: CONFIG_CLOCK_STM32_PLL_SRC_CSI=y - PLL vco input range is auto-calculated based on PLL DIVM1 -> Example for sysclock 96MHz generated with PLL from HSI CONFIG_CLOCK_STM32_PLL_SRC_HSI=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=96000000 CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y CONFIG_CLOCK_STM32_PLL_M_DIVISOR=4 CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=12 CONFIG_CLOCK_STM32_PLL_P_DIVISOR=2 CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=4 CONFIG_CLOCK_STM32_PLL_R_DIVISOR=2 Use LL_SetFlashLatency function from stm32h7xx_ll_utils.h instead to setup the correct latency. Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
2020-07-09 21:42:46 +02:00
#if !defined(CONFIG_CPU_CORTEX_M4)
drivers: clock_control: stm32h7 change set flash latency Updated flash latency setting to comply with common stm32 implementation and datasheet. Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
2020-07-29 20:34:46 +02:00
static inline uint32_t get_pllsrc_frequency(void)
{
switch (LL_RCC_PLL_GetSource()) {
case LL_RCC_PLLSOURCE_HSI:
return HSI_VALUE;
case LL_RCC_PLLSOURCE_CSI:
return CSI_VALUE;
case LL_RCC_PLLSOURCE_HSE:
return HSE_VALUE;
case LL_RCC_PLLSOURCE_NONE:
default:
return 0;
}
}
static uint32_t get_hclk_frequency(void)
{
uint32_t sysclk = 0;
uint32_t hpre = 0;
drivers: clock_control: stm32h7 add HSI divisor support Add HSI divisor support for clock tree configuration. Removed HSI calibration trimming to comply with common STM32 implementation and use reset default configuration instead. Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
2020-07-30 09:45:32 +02:00
uint32_t hsidiv = 0;
/* Get the current HSI divider */
switch (LL_RCC_HSI_GetDivider()) {
case LL_RCC_HSI_DIV2:
hsidiv = 2;
break;
case LL_RCC_HSI_DIV4:
hsidiv = 4;
break;
case LL_RCC_HSI_DIV8:
hsidiv = 8;
break;
case LL_RCC_HSI_DIV1:
default:
hsidiv = 1;
break;
}
drivers: clock_control: stm32h7 change set flash latency Updated flash latency setting to comply with common stm32 implementation and datasheet. Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
2020-07-29 20:34:46 +02:00
/* Get the current system clock source */
switch (LL_RCC_GetSysClkSource()) {
case LL_RCC_SYS_CLKSOURCE_STATUS_HSI:
drivers: clock_control: stm32h7 add HSI divisor support Add HSI divisor support for clock tree configuration. Removed HSI calibration trimming to comply with common STM32 implementation and use reset default configuration instead. Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
2020-07-30 09:45:32 +02:00
sysclk = HSI_VALUE/hsidiv;
drivers: clock_control: stm32h7 change set flash latency Updated flash latency setting to comply with common stm32 implementation and datasheet. Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
2020-07-29 20:34:46 +02:00
break;
case LL_RCC_SYS_CLKSOURCE_STATUS_CSI:
sysclk = CSI_VALUE;
break;
case LL_RCC_SYS_CLKSOURCE_STATUS_HSE:
sysclk = HSE_VALUE;
break;
case LL_RCC_SYS_CLKSOURCE_STATUS_PLL1:
sysclk = PLLP_FREQ(get_pllsrc_frequency(),
LL_RCC_PLL1_GetM(),
LL_RCC_PLL1_GetN(),
LL_RCC_PLL1_GetP());
break;
}
/* AHB/HCLK clock is sysclk/HPRE AHB prescaler*/
switch (LL_RCC_GetAHBPrescaler()) {
case LL_RCC_AHB_DIV_1:
hpre = 1;
break;
case LL_RCC_AHB_DIV_2:
hpre = 2;
break;
case LL_RCC_AHB_DIV_4:
hpre = 4;
break;
case LL_RCC_AHB_DIV_8:
hpre = 8;
break;
case LL_RCC_AHB_DIV_16:
hpre = 16;
break;
case LL_RCC_AHB_DIV_64:
hpre = 64;
break;
case LL_RCC_AHB_DIV_128:
hpre = 128;
break;
case LL_RCC_AHB_DIV_256:
hpre = 256;
break;
case LL_RCC_AHB_DIV_512:
hpre = 512;
break;
default:
hpre = 1;
break;
}
return get_bus_clock(sysclk, hpre);
}
drivers: clock_control: stm32h7: Add HSE,HSI,CSI,PLL sysclk opt. Add HSE,HSI,CSI,PLL as system clock options. Also add correct configuration of the PLL. New sysclk options: - HSI with: CONFIG_CLOCK_STM32_SYSCLK_SRC_HSI=y - HSE with: CONFIG_CLOCK_STM32_SYSCLK_SRC_HSE=y - CSI with: CONFIG_CLOCK_STM32_SYSCLK_SRC_CSI=y Existing sysclk options: - PLL with: CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y PLL clock options: - More PLL source clocks: Existing: 1. HSE with: CONFIG_CLOCK_STM32_PLL_SRC_HSE=y New: 2. HSI with: CONFIG_CLOCK_STM32_PLL_SRC_HSI=y 3. CSI with: CONFIG_CLOCK_STM32_PLL_SRC_CSI=y - PLL vco input range is auto-calculated based on PLL DIVM1 -> Example for sysclock 96MHz generated with PLL from HSI CONFIG_CLOCK_STM32_PLL_SRC_HSI=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=96000000 CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y CONFIG_CLOCK_STM32_PLL_M_DIVISOR=4 CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=12 CONFIG_CLOCK_STM32_PLL_P_DIVISOR=2 CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=4 CONFIG_CLOCK_STM32_PLL_R_DIVISOR=2 Use LL_SetFlashLatency function from stm32h7xx_ll_utils.h instead to setup the correct latency. Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
2020-07-09 21:42:46 +02:00
static int32_t prepare_regulator_voltage_scale(void)
{
/* Make sure to put the CPU in highest Voltage scale during clock configuration */
LL_PWR_ConfigSupply(LL_PWR_LDO_SUPPLY);
/* Highest voltage is SCALE0 */
LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE0);
return 0;
}
static int32_t optimize_regulator_voltage_scale(uint32_t sysclk_freq)
{
/* After sysclock is configured, tweak the voltage scale down */
/* to reduce power consumption */
/* Needs some smart work to configure properly */
/* LL_PWR_REGULATOR_SCALE3 is lowest power consumption */
/* Must be done in accordance to the Maximum allowed frequency vs VOS*/
/* See RM0433 page 352 for more details */
LL_PWR_ConfigSupply(LL_PWR_LDO_SUPPLY);
LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE0);
return 0;
}
drivers: clock_control: stm32h7: Use dts based configuration macros Update stm32h7 clock_control driver to make use of macros allowing dts based configuration in coexistance with existing Kconfig method. Note: Use of IS_ENABLED is removed as it generates warnings in checkpatch. This checkpatch behavior needs to be reviewed but may first require a little clean up of IS_ENABLED macro. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-04-29 14:41:58 +02:00
#if STM32_PLL_SRC_HSE || \
STM32_PLL_SRC_HSI || \
STM32_PLL_SRC_CSI || \
STM32_PLL3_ENABLE
drivers: clock_control: stm32h7: Add HSE,HSI,CSI,PLL sysclk opt. Add HSE,HSI,CSI,PLL as system clock options. Also add correct configuration of the PLL. New sysclk options: - HSI with: CONFIG_CLOCK_STM32_SYSCLK_SRC_HSI=y - HSE with: CONFIG_CLOCK_STM32_SYSCLK_SRC_HSE=y - CSI with: CONFIG_CLOCK_STM32_SYSCLK_SRC_CSI=y Existing sysclk options: - PLL with: CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y PLL clock options: - More PLL source clocks: Existing: 1. HSE with: CONFIG_CLOCK_STM32_PLL_SRC_HSE=y New: 2. HSI with: CONFIG_CLOCK_STM32_PLL_SRC_HSI=y 3. CSI with: CONFIG_CLOCK_STM32_PLL_SRC_CSI=y - PLL vco input range is auto-calculated based on PLL DIVM1 -> Example for sysclock 96MHz generated with PLL from HSI CONFIG_CLOCK_STM32_PLL_SRC_HSI=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=96000000 CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y CONFIG_CLOCK_STM32_PLL_M_DIVISOR=4 CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=12 CONFIG_CLOCK_STM32_PLL_P_DIVISOR=2 CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=4 CONFIG_CLOCK_STM32_PLL_R_DIVISOR=2 Use LL_SetFlashLatency function from stm32h7xx_ll_utils.h instead to setup the correct latency. Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
2020-07-09 21:42:46 +02:00
drivers: clock_control: provide function to compute PLL VCO input range Provide a utility function to compute PLL VCO input range so that it can be re-used for other PLLs. Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2020-12-05 17:28:30 +01:00
static int get_vco_input_range(uint32_t m_div, uint32_t *range)
{
uint32_t vco_freq;
vco_freq = PLLSRC_FREQ / m_div;
drivers: clock_control: add support for PLL3 on STM32 H7 Add support for enabling and configuring PLL3 on STM32 H7 series. PLL3 is used as a clock source by certain peripherals, e.g. LTDC. Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2020-12-19 11:24:43 +01:00
if (MHZ(1) <= vco_freq && vco_freq <= MHZ(2)) {
drivers: clock_control: provide function to compute PLL VCO input range Provide a utility function to compute PLL VCO input range so that it can be re-used for other PLLs. Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2020-12-05 17:28:30 +01:00
*range = LL_RCC_PLLINPUTRANGE_1_2;
drivers: clock_control: add support for PLL3 on STM32 H7 Add support for enabling and configuring PLL3 on STM32 H7 series. PLL3 is used as a clock source by certain peripherals, e.g. LTDC. Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2020-12-19 11:24:43 +01:00
} else if (MHZ(2) < vco_freq && vco_freq <= MHZ(4)) {
drivers: clock_control: provide function to compute PLL VCO input range Provide a utility function to compute PLL VCO input range so that it can be re-used for other PLLs. Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2020-12-05 17:28:30 +01:00
*range = LL_RCC_PLLINPUTRANGE_2_4;
drivers: clock_control: add support for PLL3 on STM32 H7 Add support for enabling and configuring PLL3 on STM32 H7 series. PLL3 is used as a clock source by certain peripherals, e.g. LTDC. Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2020-12-19 11:24:43 +01:00
} else if (MHZ(4) < vco_freq && vco_freq <= MHZ(8)) {
drivers: clock_control: provide function to compute PLL VCO input range Provide a utility function to compute PLL VCO input range so that it can be re-used for other PLLs. Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2020-12-05 17:28:30 +01:00
*range = LL_RCC_PLLINPUTRANGE_4_8;
drivers: clock_control: add support for PLL3 on STM32 H7 Add support for enabling and configuring PLL3 on STM32 H7 series. PLL3 is used as a clock source by certain peripherals, e.g. LTDC. Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2020-12-19 11:24:43 +01:00
} else if (MHZ(8) < vco_freq && vco_freq <= MHZ(16)) {
drivers: clock_control: provide function to compute PLL VCO input range Provide a utility function to compute PLL VCO input range so that it can be re-used for other PLLs. Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2020-12-05 17:28:30 +01:00
*range = LL_RCC_PLLINPUTRANGE_8_16;
} else {
return -ERANGE;
}
return 0;
}
static uint32_t get_vco_output_range(uint32_t vco_input_range)
drivers: clock_control: stm32h7: Add HSE,HSI,CSI,PLL sysclk opt. Add HSE,HSI,CSI,PLL as system clock options. Also add correct configuration of the PLL. New sysclk options: - HSI with: CONFIG_CLOCK_STM32_SYSCLK_SRC_HSI=y - HSE with: CONFIG_CLOCK_STM32_SYSCLK_SRC_HSE=y - CSI with: CONFIG_CLOCK_STM32_SYSCLK_SRC_CSI=y Existing sysclk options: - PLL with: CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y PLL clock options: - More PLL source clocks: Existing: 1. HSE with: CONFIG_CLOCK_STM32_PLL_SRC_HSE=y New: 2. HSI with: CONFIG_CLOCK_STM32_PLL_SRC_HSI=y 3. CSI with: CONFIG_CLOCK_STM32_PLL_SRC_CSI=y - PLL vco input range is auto-calculated based on PLL DIVM1 -> Example for sysclock 96MHz generated with PLL from HSI CONFIG_CLOCK_STM32_PLL_SRC_HSI=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=96000000 CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y CONFIG_CLOCK_STM32_PLL_M_DIVISOR=4 CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=12 CONFIG_CLOCK_STM32_PLL_P_DIVISOR=2 CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=4 CONFIG_CLOCK_STM32_PLL_R_DIVISOR=2 Use LL_SetFlashLatency function from stm32h7xx_ll_utils.h instead to setup the correct latency. Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
2020-07-09 21:42:46 +02:00
{
if (vco_input_range == LL_RCC_PLLINPUTRANGE_1_2) {
return LL_RCC_PLLVCORANGE_MEDIUM;
}
return LL_RCC_PLLVCORANGE_WIDE;
}
drivers: clock_control: stm32h7: Use dts based configuration macros Update stm32h7 clock_control driver to make use of macros allowing dts based configuration in coexistance with existing Kconfig method. Note: Use of IS_ENABLED is removed as it generates warnings in checkpatch. This checkpatch behavior needs to be reviewed but may first require a little clean up of IS_ENABLED macro. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-04-29 14:41:58 +02:00
#endif /* STM32_PLL_SRC_* */
drivers: clock_control: stm32h7: Add HSE,HSI,CSI,PLL sysclk opt. Add HSE,HSI,CSI,PLL as system clock options. Also add correct configuration of the PLL. New sysclk options: - HSI with: CONFIG_CLOCK_STM32_SYSCLK_SRC_HSI=y - HSE with: CONFIG_CLOCK_STM32_SYSCLK_SRC_HSE=y - CSI with: CONFIG_CLOCK_STM32_SYSCLK_SRC_CSI=y Existing sysclk options: - PLL with: CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y PLL clock options: - More PLL source clocks: Existing: 1. HSE with: CONFIG_CLOCK_STM32_PLL_SRC_HSE=y New: 2. HSI with: CONFIG_CLOCK_STM32_PLL_SRC_HSI=y 3. CSI with: CONFIG_CLOCK_STM32_PLL_SRC_CSI=y - PLL vco input range is auto-calculated based on PLL DIVM1 -> Example for sysclock 96MHz generated with PLL from HSI CONFIG_CLOCK_STM32_PLL_SRC_HSI=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=96000000 CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y CONFIG_CLOCK_STM32_PLL_M_DIVISOR=4 CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=12 CONFIG_CLOCK_STM32_PLL_P_DIVISOR=2 CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=4 CONFIG_CLOCK_STM32_PLL_R_DIVISOR=2 Use LL_SetFlashLatency function from stm32h7xx_ll_utils.h instead to setup the correct latency. Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
2020-07-09 21:42:46 +02:00
#endif /* ! CONFIG_CPU_CORTEX_M4 */
device: Const-ify all device driver instance pointers Now that device_api attribute is unmodified at runtime, as well as all the other attributes, it is possible to switch all device driver instance to be constant. A coccinelle rule is used for this: @r_const_dev_1 disable optional_qualifier @ @@ -struct device * +const struct device * @r_const_dev_2 disable optional_qualifier @ @@ -struct device * const +const struct device * Fixes #27399 Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2020-04-30 20:33:38 +02:00
static inline int stm32_clock_control_on(const struct device *dev,
drivers/clock_control: STM32H7 support Provide basic clock control driver for STM32H7. Bus clock activation is done through CM7 and CM4 common registers so we don't have to care to the CPU Id before accessing. Accesses are not protected for now. Only possible configuration is system clock source set to HSE driven PLL. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2019-07-01 14:12:48 +02:00
clock_control_subsys_t sub_system)
{
struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
drivers: STM32 dualcore concurrent register access protection with HSEM In case of dualcore, STM32H7, STM32W and STM32MP1, protect concurrent register write access with HSEM. Done for following drivers: clock_control, counter, flash, gpio, interrupt_controller Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
2020-06-23 09:48:07 +02:00
int rc = 0;
drivers/clock_control: STM32H7 support Provide basic clock control driver for STM32H7. Bus clock activation is done through CM7 and CM4 common registers so we don't have to care to the CPU Id before accessing. Accesses are not protected for now. Only possible configuration is system clock source set to HSE driven PLL. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2019-07-01 14:12:48 +02:00
ARG_UNUSED(dev);
drivers: clock_control: stm32h7: fix comment mistake 'bansk' Change comment word 'bansk' to 'banks'. Signed-off-by: Oliver Yang <cameledyang@pm.me>
2021-07-23 04:40:02 +02:00
/* Both cores can access banks by following LL API */
drivers/clock_control: stm32h7: Disable configuration for CM4 core On STM32H7, in Dual core configuration, we restrict configuration access to CM7 core. CM4 can access to API but not the init part of the driver. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2019-06-14 16:18:39 +02:00
/* Using "_Cn_" LL API would restrict access to one or the other */
drivers: STM32 dualcore concurrent register access protection with HSEM In case of dualcore, STM32H7, STM32W and STM32MP1, protect concurrent register write access with HSEM. Done for following drivers: clock_control, counter, flash, gpio, interrupt_controller Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
2020-06-23 09:48:07 +02:00
z_stm32_hsem_lock(CFG_HW_RCC_SEMID, HSEM_LOCK_DEFAULT_RETRY);
drivers/clock_control: STM32H7 support Provide basic clock control driver for STM32H7. Bus clock activation is done through CM7 and CM4 common registers so we don't have to care to the CPU Id before accessing. Accesses are not protected for now. Only possible configuration is system clock source set to HSE driven PLL. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2019-07-01 14:12:48 +02:00
switch (pclken->bus) {
case STM32_CLOCK_BUS_AHB1:
LL_AHB1_GRP1_EnableClock(pclken->enr);
break;
case STM32_CLOCK_BUS_AHB2:
LL_AHB2_GRP1_EnableClock(pclken->enr);
break;
case STM32_CLOCK_BUS_AHB3:
LL_AHB3_GRP1_EnableClock(pclken->enr);
break;
case STM32_CLOCK_BUS_AHB4:
LL_AHB4_GRP1_EnableClock(pclken->enr);
break;
case STM32_CLOCK_BUS_APB1:
LL_APB1_GRP1_EnableClock(pclken->enr);
break;
case STM32_CLOCK_BUS_APB1_2:
LL_APB1_GRP2_EnableClock(pclken->enr);
break;
case STM32_CLOCK_BUS_APB2:
LL_APB2_GRP1_EnableClock(pclken->enr);
break;
case STM32_CLOCK_BUS_APB3:
LL_APB3_GRP1_EnableClock(pclken->enr);
break;
case STM32_CLOCK_BUS_APB4:
LL_APB4_GRP1_EnableClock(pclken->enr);
break;
default:
drivers: STM32 dualcore concurrent register access protection with HSEM In case of dualcore, STM32H7, STM32W and STM32MP1, protect concurrent register write access with HSEM. Done for following drivers: clock_control, counter, flash, gpio, interrupt_controller Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
2020-06-23 09:48:07 +02:00
rc = -ENOTSUP;
break;
drivers/clock_control: STM32H7 support Provide basic clock control driver for STM32H7. Bus clock activation is done through CM7 and CM4 common registers so we don't have to care to the CPU Id before accessing. Accesses are not protected for now. Only possible configuration is system clock source set to HSE driven PLL. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2019-07-01 14:12:48 +02:00
}
drivers: STM32 dualcore concurrent register access protection with HSEM In case of dualcore, STM32H7, STM32W and STM32MP1, protect concurrent register write access with HSEM. Done for following drivers: clock_control, counter, flash, gpio, interrupt_controller Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
2020-06-23 09:48:07 +02:00
z_stm32_hsem_unlock(CFG_HW_RCC_SEMID);
return rc;
drivers/clock_control: STM32H7 support Provide basic clock control driver for STM32H7. Bus clock activation is done through CM7 and CM4 common registers so we don't have to care to the CPU Id before accessing. Accesses are not protected for now. Only possible configuration is system clock source set to HSE driven PLL. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2019-07-01 14:12:48 +02:00
}
device: Const-ify all device driver instance pointers Now that device_api attribute is unmodified at runtime, as well as all the other attributes, it is possible to switch all device driver instance to be constant. A coccinelle rule is used for this: @r_const_dev_1 disable optional_qualifier @ @@ -struct device * +const struct device * @r_const_dev_2 disable optional_qualifier @ @@ -struct device * const +const struct device * Fixes #27399 Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2020-04-30 20:33:38 +02:00
static inline int stm32_clock_control_off(const struct device *dev,
drivers/clock_control: STM32H7 support Provide basic clock control driver for STM32H7. Bus clock activation is done through CM7 and CM4 common registers so we don't have to care to the CPU Id before accessing. Accesses are not protected for now. Only possible configuration is system clock source set to HSE driven PLL. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2019-07-01 14:12:48 +02:00
clock_control_subsys_t sub_system)
{
struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
drivers: STM32 dualcore concurrent register access protection with HSEM In case of dualcore, STM32H7, STM32W and STM32MP1, protect concurrent register write access with HSEM. Done for following drivers: clock_control, counter, flash, gpio, interrupt_controller Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
2020-06-23 09:48:07 +02:00
int rc = 0;
drivers/clock_control: STM32H7 support Provide basic clock control driver for STM32H7. Bus clock activation is done through CM7 and CM4 common registers so we don't have to care to the CPU Id before accessing. Accesses are not protected for now. Only possible configuration is system clock source set to HSE driven PLL. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2019-07-01 14:12:48 +02:00
ARG_UNUSED(dev);
drivers: clock_control: stm32h7: fix comment mistake 'bansk' Change comment word 'bansk' to 'banks'. Signed-off-by: Oliver Yang <cameledyang@pm.me>
2021-07-23 04:40:02 +02:00
/* Both cores can access banks by following LL API */
drivers/clock_control: stm32h7: Disable configuration for CM4 core On STM32H7, in Dual core configuration, we restrict configuration access to CM7 core. CM4 can access to API but not the init part of the driver. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2019-06-14 16:18:39 +02:00
/* Using "_Cn_" LL API would restrict access to one or the other */
drivers: STM32 dualcore concurrent register access protection with HSEM In case of dualcore, STM32H7, STM32W and STM32MP1, protect concurrent register write access with HSEM. Done for following drivers: clock_control, counter, flash, gpio, interrupt_controller Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
2020-06-23 09:48:07 +02:00
z_stm32_hsem_lock(CFG_HW_RCC_SEMID, HSEM_LOCK_DEFAULT_RETRY);
drivers/clock_control: STM32H7 support Provide basic clock control driver for STM32H7. Bus clock activation is done through CM7 and CM4 common registers so we don't have to care to the CPU Id before accessing. Accesses are not protected for now. Only possible configuration is system clock source set to HSE driven PLL. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2019-07-01 14:12:48 +02:00
switch (pclken->bus) {
case STM32_CLOCK_BUS_AHB1:
LL_AHB1_GRP1_DisableClock(pclken->enr);
break;
case STM32_CLOCK_BUS_AHB2:
LL_AHB2_GRP1_DisableClock(pclken->enr);
break;
case STM32_CLOCK_BUS_AHB3:
LL_AHB3_GRP1_DisableClock(pclken->enr);
break;
case STM32_CLOCK_BUS_AHB4:
LL_AHB4_GRP1_DisableClock(pclken->enr);
break;
case STM32_CLOCK_BUS_APB1:
LL_APB1_GRP1_DisableClock(pclken->enr);
break;
case STM32_CLOCK_BUS_APB1_2:
LL_APB1_GRP2_DisableClock(pclken->enr);
break;
case STM32_CLOCK_BUS_APB2:
LL_APB2_GRP1_DisableClock(pclken->enr);
break;
case STM32_CLOCK_BUS_APB3:
LL_APB3_GRP1_DisableClock(pclken->enr);
break;
case STM32_CLOCK_BUS_APB4:
LL_APB4_GRP1_DisableClock(pclken->enr);
break;
default:
drivers: STM32 dualcore concurrent register access protection with HSEM In case of dualcore, STM32H7, STM32W and STM32MP1, protect concurrent register write access with HSEM. Done for following drivers: clock_control, counter, flash, gpio, interrupt_controller Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
2020-06-23 09:48:07 +02:00
rc = -ENOTSUP;
break;
drivers/clock_control: STM32H7 support Provide basic clock control driver for STM32H7. Bus clock activation is done through CM7 and CM4 common registers so we don't have to care to the CPU Id before accessing. Accesses are not protected for now. Only possible configuration is system clock source set to HSE driven PLL. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2019-07-01 14:12:48 +02:00
}
drivers: STM32 dualcore concurrent register access protection with HSEM In case of dualcore, STM32H7, STM32W and STM32MP1, protect concurrent register write access with HSEM. Done for following drivers: clock_control, counter, flash, gpio, interrupt_controller Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
2020-06-23 09:48:07 +02:00
z_stm32_hsem_unlock(CFG_HW_RCC_SEMID);
drivers/clock_control: STM32H7 support Provide basic clock control driver for STM32H7. Bus clock activation is done through CM7 and CM4 common registers so we don't have to care to the CPU Id before accessing. Accesses are not protected for now. Only possible configuration is system clock source set to HSE driven PLL. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2019-07-01 14:12:48 +02:00
drivers: STM32 dualcore concurrent register access protection with HSEM In case of dualcore, STM32H7, STM32W and STM32MP1, protect concurrent register write access with HSEM. Done for following drivers: clock_control, counter, flash, gpio, interrupt_controller Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
2020-06-23 09:48:07 +02:00
return rc;
drivers/clock_control: STM32H7 support Provide basic clock control driver for STM32H7. Bus clock activation is done through CM7 and CM4 common registers so we don't have to care to the CPU Id before accessing. Accesses are not protected for now. Only possible configuration is system clock source set to HSE driven PLL. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2019-07-01 14:12:48 +02:00
}
device: Const-ify all device driver instance pointers Now that device_api attribute is unmodified at runtime, as well as all the other attributes, it is possible to switch all device driver instance to be constant. A coccinelle rule is used for this: @r_const_dev_1 disable optional_qualifier @ @@ -struct device * +const struct device * @r_const_dev_2 disable optional_qualifier @ @@ -struct device * const +const struct device * Fixes #27399 Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2020-04-30 20:33:38 +02:00
static int stm32_clock_control_get_subsys_rate(const struct device *clock,
clock_control_subsys_t sub_system,
uint32_t *rate)
drivers/clock_control: STM32H7 support Provide basic clock control driver for STM32H7. Bus clock activation is done through CM7 and CM4 common registers so we don't have to care to the CPU Id before accessing. Accesses are not protected for now. Only possible configuration is system clock source set to HSE driven PLL. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2019-07-01 14:12:48 +02:00
{
struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
/*
* Get AHB Clock (= SystemCoreClock = SYSCLK/prescaler)
* SystemCoreClock is preferred to CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC
* since it will be updated after clock configuration and hence
* more likely to contain actual clock speed
*/
drivers/clock_control: stm32H7 AHB clock computation depends on core On cortex M4, AHB clock is equal to SystemCoreClock On Cortex M7, AHB clock is equal to SystemCoreClock/HPRE By the way, D1CPRE is of no use when starting from SystemCoreColck. Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
2020-04-29 15:17:30 +02:00
#if defined(CONFIG_CPU_CORTEX_M4)
zephyr: replace zephyr integer types with C99 types git grep -l 'u\(8\|16\|32\|64\)_t' | \ xargs sed -i "s/u\(8\|16\|32\|64\)_t/uint\1_t/g" git grep -l 's\(8\|16\|32\|64\)_t' | \ xargs sed -i "s/s\(8\|16\|32\|64\)_t/int\1_t/g" Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-05-27 18:26:57 +02:00
uint32_t ahb_clock = SystemCoreClock;
drivers/clock_control: stm32H7 AHB clock computation depends on core On cortex M4, AHB clock is equal to SystemCoreClock On Cortex M7, AHB clock is equal to SystemCoreClock/HPRE By the way, D1CPRE is of no use when starting from SystemCoreColck. Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
2020-04-29 15:17:30 +02:00
#else
drivers: clock_control: stm32h7: Use dts based configuration macros Update stm32h7 clock_control driver to make use of macros allowing dts based configuration in coexistance with existing Kconfig method. Note: Use of IS_ENABLED is removed as it generates warnings in checkpatch. This checkpatch behavior needs to be reviewed but may first require a little clean up of IS_ENABLED macro. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-04-29 14:41:58 +02:00
uint32_t ahb_clock = get_bus_clock(SystemCoreClock, STM32_HPRE);
drivers/clock_control: stm32H7 AHB clock computation depends on core On cortex M4, AHB clock is equal to SystemCoreClock On Cortex M7, AHB clock is equal to SystemCoreClock/HPRE By the way, D1CPRE is of no use when starting from SystemCoreColck. Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
2020-04-29 15:17:30 +02:00
#endif
drivers: clock_control: stm32h7: Use dts based configuration macros Update stm32h7 clock_control driver to make use of macros allowing dts based configuration in coexistance with existing Kconfig method. Note: Use of IS_ENABLED is removed as it generates warnings in checkpatch. This checkpatch behavior needs to be reviewed but may first require a little clean up of IS_ENABLED macro. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-04-29 14:41:58 +02:00
uint32_t apb1_clock = get_bus_clock(ahb_clock, STM32_D2PPRE1);
uint32_t apb2_clock = get_bus_clock(ahb_clock, STM32_D2PPRE2);
uint32_t apb3_clock = get_bus_clock(ahb_clock, STM32_D1PPRE);
uint32_t apb4_clock = get_bus_clock(ahb_clock, STM32_D3PPRE);
drivers/clock_control: STM32H7 support Provide basic clock control driver for STM32H7. Bus clock activation is done through CM7 and CM4 common registers so we don't have to care to the CPU Id before accessing. Accesses are not protected for now. Only possible configuration is system clock source set to HSE driven PLL. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2019-07-01 14:12:48 +02:00
ARG_UNUSED(clock);
switch (pclken->bus) {
case STM32_CLOCK_BUS_AHB1:
case STM32_CLOCK_BUS_AHB2:
case STM32_CLOCK_BUS_AHB3:
case STM32_CLOCK_BUS_AHB4:
*rate = ahb_clock;
break;
case STM32_CLOCK_BUS_APB1:
case STM32_CLOCK_BUS_APB1_2:
*rate = apb1_clock;
break;
case STM32_CLOCK_BUS_APB2:
*rate = apb2_clock;
break;
case STM32_CLOCK_BUS_APB3:
*rate = apb3_clock;
break;
case STM32_CLOCK_BUS_APB4:
*rate = apb4_clock;
break;
default:
return -ENOTSUP;
}
return 0;
}
static struct clock_control_driver_api stm32_clock_control_api = {
.on = stm32_clock_control_on,
.off = stm32_clock_control_off,
.get_rate = stm32_clock_control_get_subsys_rate,
};
device: Const-ify all device driver instance pointers Now that device_api attribute is unmodified at runtime, as well as all the other attributes, it is possible to switch all device driver instance to be constant. A coccinelle rule is used for this: @r_const_dev_1 disable optional_qualifier @ @@ -struct device * +const struct device * @r_const_dev_2 disable optional_qualifier @ @@ -struct device * const +const struct device * Fixes #27399 Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2020-04-30 20:33:38 +02:00
static int stm32_clock_control_init(const struct device *dev)
drivers/clock_control: STM32H7 support Provide basic clock control driver for STM32H7. Bus clock activation is done through CM7 and CM4 common registers so we don't have to care to the CPU Id before accessing. Accesses are not protected for now. Only possible configuration is system clock source set to HSE driven PLL. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2019-07-01 14:12:48 +02:00
{
drivers/clock_control: stm32h7: Disable configuration for CM4 core On STM32H7, in Dual core configuration, we restrict configuration access to CM7 core. CM4 can access to API but not the init part of the driver. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2019-06-14 16:18:39 +02:00
#if !defined(CONFIG_CPU_CORTEX_M4)
drivers: clock_control: stm32h7 change set flash latency Updated flash latency setting to comply with common stm32 implementation and datasheet. Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
2020-07-29 20:34:46 +02:00
uint32_t old_hclk_freq = 0;
uint32_t new_hclk_freq = 0;
drivers: clock_control: stm32h7: Add HSE,HSI,CSI,PLL sysclk opt. Add HSE,HSI,CSI,PLL as system clock options. Also add correct configuration of the PLL. New sysclk options: - HSI with: CONFIG_CLOCK_STM32_SYSCLK_SRC_HSI=y - HSE with: CONFIG_CLOCK_STM32_SYSCLK_SRC_HSE=y - CSI with: CONFIG_CLOCK_STM32_SYSCLK_SRC_CSI=y Existing sysclk options: - PLL with: CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y PLL clock options: - More PLL source clocks: Existing: 1. HSE with: CONFIG_CLOCK_STM32_PLL_SRC_HSE=y New: 2. HSI with: CONFIG_CLOCK_STM32_PLL_SRC_HSI=y 3. CSI with: CONFIG_CLOCK_STM32_PLL_SRC_CSI=y - PLL vco input range is auto-calculated based on PLL DIVM1 -> Example for sysclock 96MHz generated with PLL from HSI CONFIG_CLOCK_STM32_PLL_SRC_HSI=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=96000000 CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y CONFIG_CLOCK_STM32_PLL_M_DIVISOR=4 CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=12 CONFIG_CLOCK_STM32_PLL_P_DIVISOR=2 CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=4 CONFIG_CLOCK_STM32_PLL_R_DIVISOR=2 Use LL_SetFlashLatency function from stm32h7xx_ll_utils.h instead to setup the correct latency. Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
2020-07-09 21:42:46 +02:00
drivers: clock_control: stm32h7: Use dts based configuration macros Update stm32h7 clock_control driver to make use of macros allowing dts based configuration in coexistance with existing Kconfig method. Note: Use of IS_ENABLED is removed as it generates warnings in checkpatch. This checkpatch behavior needs to be reviewed but may first require a little clean up of IS_ENABLED macro. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-04-29 14:41:58 +02:00
#if STM32_PLL_SRC_HSE || \
STM32_PLL_SRC_HSI || \
STM32_PLL_SRC_CSI || \
STM32_PLL3_ENABLE
drivers: clock_control: stm32h7: Add HSE,HSI,CSI,PLL sysclk opt. Add HSE,HSI,CSI,PLL as system clock options. Also add correct configuration of the PLL. New sysclk options: - HSI with: CONFIG_CLOCK_STM32_SYSCLK_SRC_HSI=y - HSE with: CONFIG_CLOCK_STM32_SYSCLK_SRC_HSE=y - CSI with: CONFIG_CLOCK_STM32_SYSCLK_SRC_CSI=y Existing sysclk options: - PLL with: CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y PLL clock options: - More PLL source clocks: Existing: 1. HSE with: CONFIG_CLOCK_STM32_PLL_SRC_HSE=y New: 2. HSI with: CONFIG_CLOCK_STM32_PLL_SRC_HSI=y 3. CSI with: CONFIG_CLOCK_STM32_PLL_SRC_CSI=y - PLL vco input range is auto-calculated based on PLL DIVM1 -> Example for sysclock 96MHz generated with PLL from HSI CONFIG_CLOCK_STM32_PLL_SRC_HSI=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=96000000 CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y CONFIG_CLOCK_STM32_PLL_M_DIVISOR=4 CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=12 CONFIG_CLOCK_STM32_PLL_P_DIVISOR=2 CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=4 CONFIG_CLOCK_STM32_PLL_R_DIVISOR=2 Use LL_SetFlashLatency function from stm32h7xx_ll_utils.h instead to setup the correct latency. Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
2020-07-09 21:42:46 +02:00
drivers: clock_control: provide function to compute PLL VCO input range Provide a utility function to compute PLL VCO input range so that it can be re-used for other PLLs. Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2020-12-05 17:28:30 +01:00
int r;
uint32_t vco_input_range;
uint32_t vco_output_range;
drivers: clock_control: stm32h7: Use dts based configuration macros Update stm32h7 clock_control driver to make use of macros allowing dts based configuration in coexistance with existing Kconfig method. Note: Use of IS_ENABLED is removed as it generates warnings in checkpatch. This checkpatch behavior needs to be reviewed but may first require a little clean up of IS_ENABLED macro. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-04-29 14:41:58 +02:00
#endif /* STM32_PLL_SRC_* */
drivers: clock_control: stm32h7: Add HSE,HSI,CSI,PLL sysclk opt. Add HSE,HSI,CSI,PLL as system clock options. Also add correct configuration of the PLL. New sysclk options: - HSI with: CONFIG_CLOCK_STM32_SYSCLK_SRC_HSI=y - HSE with: CONFIG_CLOCK_STM32_SYSCLK_SRC_HSE=y - CSI with: CONFIG_CLOCK_STM32_SYSCLK_SRC_CSI=y Existing sysclk options: - PLL with: CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y PLL clock options: - More PLL source clocks: Existing: 1. HSE with: CONFIG_CLOCK_STM32_PLL_SRC_HSE=y New: 2. HSI with: CONFIG_CLOCK_STM32_PLL_SRC_HSI=y 3. CSI with: CONFIG_CLOCK_STM32_PLL_SRC_CSI=y - PLL vco input range is auto-calculated based on PLL DIVM1 -> Example for sysclock 96MHz generated with PLL from HSI CONFIG_CLOCK_STM32_PLL_SRC_HSI=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=96000000 CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y CONFIG_CLOCK_STM32_PLL_M_DIVISOR=4 CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=12 CONFIG_CLOCK_STM32_PLL_P_DIVISOR=2 CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=4 CONFIG_CLOCK_STM32_PLL_R_DIVISOR=2 Use LL_SetFlashLatency function from stm32h7xx_ll_utils.h instead to setup the correct latency. Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
2020-07-09 21:42:46 +02:00
#endif /* ! CONFIG_CPU_CORTEX_M4 */
drivers/clock_control: stm32h7: Disable configuration for CM4 core On STM32H7, in Dual core configuration, we restrict configuration access to CM7 core. CM4 can access to API but not the init part of the driver. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2019-06-14 16:18:39 +02:00
drivers: clock_control: stm32h7: Add HSE,HSI,CSI,PLL sysclk opt. Add HSE,HSI,CSI,PLL as system clock options. Also add correct configuration of the PLL. New sysclk options: - HSI with: CONFIG_CLOCK_STM32_SYSCLK_SRC_HSI=y - HSE with: CONFIG_CLOCK_STM32_SYSCLK_SRC_HSE=y - CSI with: CONFIG_CLOCK_STM32_SYSCLK_SRC_CSI=y Existing sysclk options: - PLL with: CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y PLL clock options: - More PLL source clocks: Existing: 1. HSE with: CONFIG_CLOCK_STM32_PLL_SRC_HSE=y New: 2. HSI with: CONFIG_CLOCK_STM32_PLL_SRC_HSI=y 3. CSI with: CONFIG_CLOCK_STM32_PLL_SRC_CSI=y - PLL vco input range is auto-calculated based on PLL DIVM1 -> Example for sysclock 96MHz generated with PLL from HSI CONFIG_CLOCK_STM32_PLL_SRC_HSI=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=96000000 CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y CONFIG_CLOCK_STM32_PLL_M_DIVISOR=4 CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=12 CONFIG_CLOCK_STM32_PLL_P_DIVISOR=2 CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=4 CONFIG_CLOCK_STM32_PLL_R_DIVISOR=2 Use LL_SetFlashLatency function from stm32h7xx_ll_utils.h instead to setup the correct latency. Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
2020-07-09 21:42:46 +02:00
ARG_UNUSED(dev);
#if !defined(CONFIG_CPU_CORTEX_M4)
drivers/clock_control: STM32H7 support Provide basic clock control driver for STM32H7. Bus clock activation is done through CM7 and CM4 common registers so we don't have to care to the CPU Id before accessing. Accesses are not protected for now. Only possible configuration is system clock source set to HSE driven PLL. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2019-07-01 14:12:48 +02:00
drivers: STM32 dualcore concurrent register access protection with HSEM In case of dualcore, STM32H7, STM32W and STM32MP1, protect concurrent register write access with HSEM. Done for following drivers: clock_control, counter, flash, gpio, interrupt_controller Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
2020-06-23 09:48:07 +02:00
/* HW semaphore Clock enable */
LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_HSEM);
z_stm32_hsem_lock(CFG_HW_RCC_SEMID, HSEM_LOCK_DEFAULT_RETRY);
drivers: clock_control: stm32h7: Add HSE,HSI,CSI,PLL sysclk opt. Add HSE,HSI,CSI,PLL as system clock options. Also add correct configuration of the PLL. New sysclk options: - HSI with: CONFIG_CLOCK_STM32_SYSCLK_SRC_HSI=y - HSE with: CONFIG_CLOCK_STM32_SYSCLK_SRC_HSE=y - CSI with: CONFIG_CLOCK_STM32_SYSCLK_SRC_CSI=y Existing sysclk options: - PLL with: CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y PLL clock options: - More PLL source clocks: Existing: 1. HSE with: CONFIG_CLOCK_STM32_PLL_SRC_HSE=y New: 2. HSI with: CONFIG_CLOCK_STM32_PLL_SRC_HSI=y 3. CSI with: CONFIG_CLOCK_STM32_PLL_SRC_CSI=y - PLL vco input range is auto-calculated based on PLL DIVM1 -> Example for sysclock 96MHz generated with PLL from HSI CONFIG_CLOCK_STM32_PLL_SRC_HSI=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=96000000 CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y CONFIG_CLOCK_STM32_PLL_M_DIVISOR=4 CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=12 CONFIG_CLOCK_STM32_PLL_P_DIVISOR=2 CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=4 CONFIG_CLOCK_STM32_PLL_R_DIVISOR=2 Use LL_SetFlashLatency function from stm32h7xx_ll_utils.h instead to setup the correct latency. Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
2020-07-09 21:42:46 +02:00
/* Configure Voltage scale to comply with the desired system frequency */
prepare_regulator_voltage_scale();
drivers: clock_control: stm32h7 change set flash latency Updated flash latency setting to comply with common stm32 implementation and datasheet. Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
2020-07-29 20:34:46 +02:00
/* Current hclk value */
old_hclk_freq = get_hclk_frequency();
/* AHB is HCLK clock to configure */
new_hclk_freq = get_bus_clock(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC,
drivers: clock_control: stm32h7: Use dts based configuration macros Update stm32h7 clock_control driver to make use of macros allowing dts based configuration in coexistance with existing Kconfig method. Note: Use of IS_ENABLED is removed as it generates warnings in checkpatch. This checkpatch behavior needs to be reviewed but may first require a little clean up of IS_ENABLED macro. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-04-29 14:41:58 +02:00
STM32_HPRE);
drivers: clock_control: stm32h7 change set flash latency Updated flash latency setting to comply with common stm32 implementation and datasheet. Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
2020-07-29 20:34:46 +02:00
/* Set flash latency */
/* AHB/AXI/HCLK clock is SYSCLK / HPRE */
/* If freq increases, set flash latency before any clock setting */
if (new_hclk_freq > old_hclk_freq) {
LL_SetFlashLatency(new_hclk_freq);
}
drivers: clock_control: stm32h7: Add HSE,HSI,CSI,PLL sysclk opt. Add HSE,HSI,CSI,PLL as system clock options. Also add correct configuration of the PLL. New sysclk options: - HSI with: CONFIG_CLOCK_STM32_SYSCLK_SRC_HSI=y - HSE with: CONFIG_CLOCK_STM32_SYSCLK_SRC_HSE=y - CSI with: CONFIG_CLOCK_STM32_SYSCLK_SRC_CSI=y Existing sysclk options: - PLL with: CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y PLL clock options: - More PLL source clocks: Existing: 1. HSE with: CONFIG_CLOCK_STM32_PLL_SRC_HSE=y New: 2. HSI with: CONFIG_CLOCK_STM32_PLL_SRC_HSI=y 3. CSI with: CONFIG_CLOCK_STM32_PLL_SRC_CSI=y - PLL vco input range is auto-calculated based on PLL DIVM1 -> Example for sysclock 96MHz generated with PLL from HSI CONFIG_CLOCK_STM32_PLL_SRC_HSI=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=96000000 CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y CONFIG_CLOCK_STM32_PLL_M_DIVISOR=4 CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=12 CONFIG_CLOCK_STM32_PLL_P_DIVISOR=2 CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=4 CONFIG_CLOCK_STM32_PLL_R_DIVISOR=2 Use LL_SetFlashLatency function from stm32h7xx_ll_utils.h instead to setup the correct latency. Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
2020-07-09 21:42:46 +02:00
/* Configure PLL source */
/* Can be HSE , HSI 64Mhz/HSIDIV, CSI 4MHz*/
drivers: clock_control: stm32h7: Use dts based configuration macros Update stm32h7 clock_control driver to make use of macros allowing dts based configuration in coexistance with existing Kconfig method. Note: Use of IS_ENABLED is removed as it generates warnings in checkpatch. This checkpatch behavior needs to be reviewed but may first require a little clean up of IS_ENABLED macro. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-04-29 14:41:58 +02:00
#if STM32_PLL_SRC_HSE
drivers/clock_control: STM32H7 support Provide basic clock control driver for STM32H7. Bus clock activation is done through CM7 and CM4 common registers so we don't have to care to the CPU Id before accessing. Accesses are not protected for now. Only possible configuration is system clock source set to HSE driven PLL. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2019-07-01 14:12:48 +02:00
drivers: clock_control: stm32h7: Use dts based configuration macros Update stm32h7 clock_control driver to make use of macros allowing dts based configuration in coexistance with existing Kconfig method. Note: Use of IS_ENABLED is removed as it generates warnings in checkpatch. This checkpatch behavior needs to be reviewed but may first require a little clean up of IS_ENABLED macro. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-04-29 14:41:58 +02:00
#if STM32_HSE_BYPASS
LL_RCC_HSE_EnableBypass();
#else
LL_RCC_HSE_DisableBypass();
#endif
drivers/clock_control: STM32H7 support Provide basic clock control driver for STM32H7. Bus clock activation is done through CM7 and CM4 common registers so we don't have to care to the CPU Id before accessing. Accesses are not protected for now. Only possible configuration is system clock source set to HSE driven PLL. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2019-07-01 14:12:48 +02:00
/* Enable HSE oscillator */
LL_RCC_HSE_Enable();
while (LL_RCC_HSE_IsReady() != 1) {
}
/* Main PLL configuration and activation */
LL_RCC_PLL_SetSource(LL_RCC_PLLSOURCE_HSE);
drivers: clock_control: stm32h7: Add HSE,HSI,CSI,PLL sysclk opt. Add HSE,HSI,CSI,PLL as system clock options. Also add correct configuration of the PLL. New sysclk options: - HSI with: CONFIG_CLOCK_STM32_SYSCLK_SRC_HSI=y - HSE with: CONFIG_CLOCK_STM32_SYSCLK_SRC_HSE=y - CSI with: CONFIG_CLOCK_STM32_SYSCLK_SRC_CSI=y Existing sysclk options: - PLL with: CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y PLL clock options: - More PLL source clocks: Existing: 1. HSE with: CONFIG_CLOCK_STM32_PLL_SRC_HSE=y New: 2. HSI with: CONFIG_CLOCK_STM32_PLL_SRC_HSI=y 3. CSI with: CONFIG_CLOCK_STM32_PLL_SRC_CSI=y - PLL vco input range is auto-calculated based on PLL DIVM1 -> Example for sysclock 96MHz generated with PLL from HSI CONFIG_CLOCK_STM32_PLL_SRC_HSI=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=96000000 CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y CONFIG_CLOCK_STM32_PLL_M_DIVISOR=4 CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=12 CONFIG_CLOCK_STM32_PLL_P_DIVISOR=2 CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=4 CONFIG_CLOCK_STM32_PLL_R_DIVISOR=2 Use LL_SetFlashLatency function from stm32h7xx_ll_utils.h instead to setup the correct latency. Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
2020-07-09 21:42:46 +02:00
drivers: clock_control: stm32h7: Use dts based configuration macros Update stm32h7 clock_control driver to make use of macros allowing dts based configuration in coexistance with existing Kconfig method. Note: Use of IS_ENABLED is removed as it generates warnings in checkpatch. This checkpatch behavior needs to be reviewed but may first require a little clean up of IS_ENABLED macro. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-04-29 14:41:58 +02:00
#elif STM32_PLL_SRC_CSI
drivers: clock_control: stm32h7: Add HSE,HSI,CSI,PLL sysclk opt. Add HSE,HSI,CSI,PLL as system clock options. Also add correct configuration of the PLL. New sysclk options: - HSI with: CONFIG_CLOCK_STM32_SYSCLK_SRC_HSI=y - HSE with: CONFIG_CLOCK_STM32_SYSCLK_SRC_HSE=y - CSI with: CONFIG_CLOCK_STM32_SYSCLK_SRC_CSI=y Existing sysclk options: - PLL with: CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y PLL clock options: - More PLL source clocks: Existing: 1. HSE with: CONFIG_CLOCK_STM32_PLL_SRC_HSE=y New: 2. HSI with: CONFIG_CLOCK_STM32_PLL_SRC_HSI=y 3. CSI with: CONFIG_CLOCK_STM32_PLL_SRC_CSI=y - PLL vco input range is auto-calculated based on PLL DIVM1 -> Example for sysclock 96MHz generated with PLL from HSI CONFIG_CLOCK_STM32_PLL_SRC_HSI=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=96000000 CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y CONFIG_CLOCK_STM32_PLL_M_DIVISOR=4 CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=12 CONFIG_CLOCK_STM32_PLL_P_DIVISOR=2 CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=4 CONFIG_CLOCK_STM32_PLL_R_DIVISOR=2 Use LL_SetFlashLatency function from stm32h7xx_ll_utils.h instead to setup the correct latency. Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
2020-07-09 21:42:46 +02:00
/* Support for CSI oscillator */
LL_RCC_CSI_Enable();
while (LL_RCC_CSI_IsReady() != 1) {
}
/* Main PLL configuration and activation */
LL_RCC_PLL_SetSource(LL_RCC_PLLSOURCE_CSI);
drivers: clock_control: stm32h7: Use dts based configuration macros Update stm32h7 clock_control driver to make use of macros allowing dts based configuration in coexistance with existing Kconfig method. Note: Use of IS_ENABLED is removed as it generates warnings in checkpatch. This checkpatch behavior needs to be reviewed but may first require a little clean up of IS_ENABLED macro. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-04-29 14:41:58 +02:00
#elif STM32_PLL_SRC_HSI
drivers: clock_control: stm32h7: Add HSE,HSI,CSI,PLL sysclk opt. Add HSE,HSI,CSI,PLL as system clock options. Also add correct configuration of the PLL. New sysclk options: - HSI with: CONFIG_CLOCK_STM32_SYSCLK_SRC_HSI=y - HSE with: CONFIG_CLOCK_STM32_SYSCLK_SRC_HSE=y - CSI with: CONFIG_CLOCK_STM32_SYSCLK_SRC_CSI=y Existing sysclk options: - PLL with: CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y PLL clock options: - More PLL source clocks: Existing: 1. HSE with: CONFIG_CLOCK_STM32_PLL_SRC_HSE=y New: 2. HSI with: CONFIG_CLOCK_STM32_PLL_SRC_HSI=y 3. CSI with: CONFIG_CLOCK_STM32_PLL_SRC_CSI=y - PLL vco input range is auto-calculated based on PLL DIVM1 -> Example for sysclock 96MHz generated with PLL from HSI CONFIG_CLOCK_STM32_PLL_SRC_HSI=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=96000000 CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y CONFIG_CLOCK_STM32_PLL_M_DIVISOR=4 CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=12 CONFIG_CLOCK_STM32_PLL_P_DIVISOR=2 CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=4 CONFIG_CLOCK_STM32_PLL_R_DIVISOR=2 Use LL_SetFlashLatency function from stm32h7xx_ll_utils.h instead to setup the correct latency. Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
2020-07-09 21:42:46 +02:00
/* By default choose HSI as PLL clock source */
/* Enable HSI oscillator */
LL_RCC_HSI_Enable();
while (LL_RCC_HSI_IsReady() != 1) {
}
drivers: clock_control: stm32h7 add HSI divisor support Add HSI divisor support for clock tree configuration. Removed HSI calibration trimming to comply with common STM32 implementation and use reset default configuration instead. Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
2020-07-30 09:45:32 +02:00
/* HSI divider configuration */
drivers: clock_control: stm32h7: Use dts based configuration macros Update stm32h7 clock_control driver to make use of macros allowing dts based configuration in coexistance with existing Kconfig method. Note: Use of IS_ENABLED is removed as it generates warnings in checkpatch. This checkpatch behavior needs to be reviewed but may first require a little clean up of IS_ENABLED macro. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-04-29 14:41:58 +02:00
LL_RCC_HSI_SetDivider(hsi_divider(STM32_HSI_DIVISOR));
drivers: clock_control: stm32h7: Add HSE,HSI,CSI,PLL sysclk opt. Add HSE,HSI,CSI,PLL as system clock options. Also add correct configuration of the PLL. New sysclk options: - HSI with: CONFIG_CLOCK_STM32_SYSCLK_SRC_HSI=y - HSE with: CONFIG_CLOCK_STM32_SYSCLK_SRC_HSE=y - CSI with: CONFIG_CLOCK_STM32_SYSCLK_SRC_CSI=y Existing sysclk options: - PLL with: CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y PLL clock options: - More PLL source clocks: Existing: 1. HSE with: CONFIG_CLOCK_STM32_PLL_SRC_HSE=y New: 2. HSI with: CONFIG_CLOCK_STM32_PLL_SRC_HSI=y 3. CSI with: CONFIG_CLOCK_STM32_PLL_SRC_CSI=y - PLL vco input range is auto-calculated based on PLL DIVM1 -> Example for sysclock 96MHz generated with PLL from HSI CONFIG_CLOCK_STM32_PLL_SRC_HSI=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=96000000 CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y CONFIG_CLOCK_STM32_PLL_M_DIVISOR=4 CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=12 CONFIG_CLOCK_STM32_PLL_P_DIVISOR=2 CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=4 CONFIG_CLOCK_STM32_PLL_R_DIVISOR=2 Use LL_SetFlashLatency function from stm32h7xx_ll_utils.h instead to setup the correct latency. Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
2020-07-09 21:42:46 +02:00
/* Main PLL configuration and activation */
LL_RCC_PLL_SetSource(LL_RCC_PLLSOURCE_HSI);
drivers/clock_control: STM32H7 support Provide basic clock control driver for STM32H7. Bus clock activation is done through CM7 and CM4 common registers so we don't have to care to the CPU Id before accessing. Accesses are not protected for now. Only possible configuration is system clock source set to HSE driven PLL. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2019-07-01 14:12:48 +02:00
#else
drivers: clock_control: stm32h7: Add HSE,HSI,CSI,PLL sysclk opt. Add HSE,HSI,CSI,PLL as system clock options. Also add correct configuration of the PLL. New sysclk options: - HSI with: CONFIG_CLOCK_STM32_SYSCLK_SRC_HSI=y - HSE with: CONFIG_CLOCK_STM32_SYSCLK_SRC_HSE=y - CSI with: CONFIG_CLOCK_STM32_SYSCLK_SRC_CSI=y Existing sysclk options: - PLL with: CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y PLL clock options: - More PLL source clocks: Existing: 1. HSE with: CONFIG_CLOCK_STM32_PLL_SRC_HSE=y New: 2. HSI with: CONFIG_CLOCK_STM32_PLL_SRC_HSI=y 3. CSI with: CONFIG_CLOCK_STM32_PLL_SRC_CSI=y - PLL vco input range is auto-calculated based on PLL DIVM1 -> Example for sysclock 96MHz generated with PLL from HSI CONFIG_CLOCK_STM32_PLL_SRC_HSI=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=96000000 CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y CONFIG_CLOCK_STM32_PLL_M_DIVISOR=4 CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=12 CONFIG_CLOCK_STM32_PLL_P_DIVISOR=2 CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=4 CONFIG_CLOCK_STM32_PLL_R_DIVISOR=2 Use LL_SetFlashLatency function from stm32h7xx_ll_utils.h instead to setup the correct latency. Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
2020-07-09 21:42:46 +02:00
/* No clock source selected for PLL, by default, disable the PLL */
LL_RCC_PLL_SetSource(LL_RCC_PLLSOURCE_NONE);
#endif
/* Configure the PLL dividers/multipliers only if PLL source is configured */
drivers: clock_control: stm32h7: Use dts based configuration macros Update stm32h7 clock_control driver to make use of macros allowing dts based configuration in coexistance with existing Kconfig method. Note: Use of IS_ENABLED is removed as it generates warnings in checkpatch. This checkpatch behavior needs to be reviewed but may first require a little clean up of IS_ENABLED macro. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-04-29 14:41:58 +02:00
#if STM32_PLL_SRC_HSE || \
STM32_PLL_SRC_HSI || \
STM32_PLL_SRC_CSI
drivers: clock_control: stm32h7: Add HSE,HSI,CSI,PLL sysclk opt. Add HSE,HSI,CSI,PLL as system clock options. Also add correct configuration of the PLL. New sysclk options: - HSI with: CONFIG_CLOCK_STM32_SYSCLK_SRC_HSI=y - HSE with: CONFIG_CLOCK_STM32_SYSCLK_SRC_HSE=y - CSI with: CONFIG_CLOCK_STM32_SYSCLK_SRC_CSI=y Existing sysclk options: - PLL with: CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y PLL clock options: - More PLL source clocks: Existing: 1. HSE with: CONFIG_CLOCK_STM32_PLL_SRC_HSE=y New: 2. HSI with: CONFIG_CLOCK_STM32_PLL_SRC_HSI=y 3. CSI with: CONFIG_CLOCK_STM32_PLL_SRC_CSI=y - PLL vco input range is auto-calculated based on PLL DIVM1 -> Example for sysclock 96MHz generated with PLL from HSI CONFIG_CLOCK_STM32_PLL_SRC_HSI=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=96000000 CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y CONFIG_CLOCK_STM32_PLL_M_DIVISOR=4 CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=12 CONFIG_CLOCK_STM32_PLL_P_DIVISOR=2 CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=4 CONFIG_CLOCK_STM32_PLL_R_DIVISOR=2 Use LL_SetFlashLatency function from stm32h7xx_ll_utils.h instead to setup the correct latency. Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
2020-07-09 21:42:46 +02:00
drivers: clock_control: stm32h7: Use dts based configuration macros Update stm32h7 clock_control driver to make use of macros allowing dts based configuration in coexistance with existing Kconfig method. Note: Use of IS_ENABLED is removed as it generates warnings in checkpatch. This checkpatch behavior needs to be reviewed but may first require a little clean up of IS_ENABLED macro. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-04-29 14:41:58 +02:00
r = get_vco_input_range(STM32_PLL_M_DIVISOR, &vco_input_range);
drivers: clock_control: provide function to compute PLL VCO input range Provide a utility function to compute PLL VCO input range so that it can be re-used for other PLLs. Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2020-12-05 17:28:30 +01:00
if (r < 0) {
return r;
}
vco_output_range = get_vco_output_range(vco_input_range);
drivers/clock_control: STM32H7 support Provide basic clock control driver for STM32H7. Bus clock activation is done through CM7 and CM4 common registers so we don't have to care to the CPU Id before accessing. Accesses are not protected for now. Only possible configuration is system clock source set to HSE driven PLL. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2019-07-01 14:12:48 +02:00
/* Configure PLL1 */
drivers: clock_control: stm32h7: Add HSE,HSI,CSI,PLL sysclk opt. Add HSE,HSI,CSI,PLL as system clock options. Also add correct configuration of the PLL. New sysclk options: - HSI with: CONFIG_CLOCK_STM32_SYSCLK_SRC_HSI=y - HSE with: CONFIG_CLOCK_STM32_SYSCLK_SRC_HSE=y - CSI with: CONFIG_CLOCK_STM32_SYSCLK_SRC_CSI=y Existing sysclk options: - PLL with: CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y PLL clock options: - More PLL source clocks: Existing: 1. HSE with: CONFIG_CLOCK_STM32_PLL_SRC_HSE=y New: 2. HSI with: CONFIG_CLOCK_STM32_PLL_SRC_HSI=y 3. CSI with: CONFIG_CLOCK_STM32_PLL_SRC_CSI=y - PLL vco input range is auto-calculated based on PLL DIVM1 -> Example for sysclock 96MHz generated with PLL from HSI CONFIG_CLOCK_STM32_PLL_SRC_HSI=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=96000000 CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y CONFIG_CLOCK_STM32_PLL_M_DIVISOR=4 CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=12 CONFIG_CLOCK_STM32_PLL_P_DIVISOR=2 CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=4 CONFIG_CLOCK_STM32_PLL_R_DIVISOR=2 Use LL_SetFlashLatency function from stm32h7xx_ll_utils.h instead to setup the correct latency. Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
2020-07-09 21:42:46 +02:00
/* According to the RM0433 datasheet */
/* Select clock source */
/* Init pre divider DIVM */
drivers: clock_control: stm32h7: Use dts based configuration macros Update stm32h7 clock_control driver to make use of macros allowing dts based configuration in coexistance with existing Kconfig method. Note: Use of IS_ENABLED is removed as it generates warnings in checkpatch. This checkpatch behavior needs to be reviewed but may first require a little clean up of IS_ENABLED macro. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-04-29 14:41:58 +02:00
LL_RCC_PLL1_SetM(STM32_PLL_M_DIVISOR);
drivers: clock_control: stm32h7: Add HSE,HSI,CSI,PLL sysclk opt. Add HSE,HSI,CSI,PLL as system clock options. Also add correct configuration of the PLL. New sysclk options: - HSI with: CONFIG_CLOCK_STM32_SYSCLK_SRC_HSI=y - HSE with: CONFIG_CLOCK_STM32_SYSCLK_SRC_HSE=y - CSI with: CONFIG_CLOCK_STM32_SYSCLK_SRC_CSI=y Existing sysclk options: - PLL with: CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y PLL clock options: - More PLL source clocks: Existing: 1. HSE with: CONFIG_CLOCK_STM32_PLL_SRC_HSE=y New: 2. HSI with: CONFIG_CLOCK_STM32_PLL_SRC_HSI=y 3. CSI with: CONFIG_CLOCK_STM32_PLL_SRC_CSI=y - PLL vco input range is auto-calculated based on PLL DIVM1 -> Example for sysclock 96MHz generated with PLL from HSI CONFIG_CLOCK_STM32_PLL_SRC_HSI=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=96000000 CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y CONFIG_CLOCK_STM32_PLL_M_DIVISOR=4 CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=12 CONFIG_CLOCK_STM32_PLL_P_DIVISOR=2 CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=4 CONFIG_CLOCK_STM32_PLL_R_DIVISOR=2 Use LL_SetFlashLatency function from stm32h7xx_ll_utils.h instead to setup the correct latency. Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
2020-07-09 21:42:46 +02:00
/* Config PLL */
/* VCO sel, VCO range */
drivers: clock_control: provide function to compute PLL VCO input range Provide a utility function to compute PLL VCO input range so that it can be re-used for other PLLs. Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2020-12-05 17:28:30 +01:00
LL_RCC_PLL1_SetVCOInputRange(vco_input_range);
drivers: clock_control: stm32h7: Add HSE,HSI,CSI,PLL sysclk opt. Add HSE,HSI,CSI,PLL as system clock options. Also add correct configuration of the PLL. New sysclk options: - HSI with: CONFIG_CLOCK_STM32_SYSCLK_SRC_HSI=y - HSE with: CONFIG_CLOCK_STM32_SYSCLK_SRC_HSE=y - CSI with: CONFIG_CLOCK_STM32_SYSCLK_SRC_CSI=y Existing sysclk options: - PLL with: CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y PLL clock options: - More PLL source clocks: Existing: 1. HSE with: CONFIG_CLOCK_STM32_PLL_SRC_HSE=y New: 2. HSI with: CONFIG_CLOCK_STM32_PLL_SRC_HSI=y 3. CSI with: CONFIG_CLOCK_STM32_PLL_SRC_CSI=y - PLL vco input range is auto-calculated based on PLL DIVM1 -> Example for sysclock 96MHz generated with PLL from HSI CONFIG_CLOCK_STM32_PLL_SRC_HSI=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=96000000 CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y CONFIG_CLOCK_STM32_PLL_M_DIVISOR=4 CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=12 CONFIG_CLOCK_STM32_PLL_P_DIVISOR=2 CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=4 CONFIG_CLOCK_STM32_PLL_R_DIVISOR=2 Use LL_SetFlashLatency function from stm32h7xx_ll_utils.h instead to setup the correct latency. Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
2020-07-09 21:42:46 +02:00
LL_RCC_PLL1_SetVCOOutputRange(vco_output_range);
/* FRACN disable DIVP,DIVQ,DIVR enable*/
LL_RCC_PLL1FRACN_Disable();
drivers/clock_control: STM32H7 support Provide basic clock control driver for STM32H7. Bus clock activation is done through CM7 and CM4 common registers so we don't have to care to the CPU Id before accessing. Accesses are not protected for now. Only possible configuration is system clock source set to HSE driven PLL. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2019-07-01 14:12:48 +02:00
LL_RCC_PLL1P_Enable();
LL_RCC_PLL1Q_Enable();
LL_RCC_PLL1R_Enable();
drivers: clock_control: stm32h7: Add HSE,HSI,CSI,PLL sysclk opt. Add HSE,HSI,CSI,PLL as system clock options. Also add correct configuration of the PLL. New sysclk options: - HSI with: CONFIG_CLOCK_STM32_SYSCLK_SRC_HSI=y - HSE with: CONFIG_CLOCK_STM32_SYSCLK_SRC_HSE=y - CSI with: CONFIG_CLOCK_STM32_SYSCLK_SRC_CSI=y Existing sysclk options: - PLL with: CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y PLL clock options: - More PLL source clocks: Existing: 1. HSE with: CONFIG_CLOCK_STM32_PLL_SRC_HSE=y New: 2. HSI with: CONFIG_CLOCK_STM32_PLL_SRC_HSI=y 3. CSI with: CONFIG_CLOCK_STM32_PLL_SRC_CSI=y - PLL vco input range is auto-calculated based on PLL DIVM1 -> Example for sysclock 96MHz generated with PLL from HSI CONFIG_CLOCK_STM32_PLL_SRC_HSI=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=96000000 CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y CONFIG_CLOCK_STM32_PLL_M_DIVISOR=4 CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=12 CONFIG_CLOCK_STM32_PLL_P_DIVISOR=2 CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=4 CONFIG_CLOCK_STM32_PLL_R_DIVISOR=2 Use LL_SetFlashLatency function from stm32h7xx_ll_utils.h instead to setup the correct latency. Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
2020-07-09 21:42:46 +02:00
/* DIVN,DIVP,DIVQ,DIVR div*/
drivers: clock_control: stm32h7: Use dts based configuration macros Update stm32h7 clock_control driver to make use of macros allowing dts based configuration in coexistance with existing Kconfig method. Note: Use of IS_ENABLED is removed as it generates warnings in checkpatch. This checkpatch behavior needs to be reviewed but may first require a little clean up of IS_ENABLED macro. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-04-29 14:41:58 +02:00
LL_RCC_PLL1_SetN(STM32_PLL_N_MULTIPLIER);
LL_RCC_PLL1_SetP(STM32_PLL_P_DIVISOR);
LL_RCC_PLL1_SetQ(STM32_PLL_Q_DIVISOR);
LL_RCC_PLL1_SetR(STM32_PLL_R_DIVISOR);
drivers/clock_control: STM32H7 support Provide basic clock control driver for STM32H7. Bus clock activation is done through CM7 and CM4 common registers so we don't have to care to the CPU Id before accessing. Accesses are not protected for now. Only possible configuration is system clock source set to HSE driven PLL. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2019-07-01 14:12:48 +02:00
drivers: clock_control: stm32h7: Add HSE,HSI,CSI,PLL sysclk opt. Add HSE,HSI,CSI,PLL as system clock options. Also add correct configuration of the PLL. New sysclk options: - HSI with: CONFIG_CLOCK_STM32_SYSCLK_SRC_HSI=y - HSE with: CONFIG_CLOCK_STM32_SYSCLK_SRC_HSE=y - CSI with: CONFIG_CLOCK_STM32_SYSCLK_SRC_CSI=y Existing sysclk options: - PLL with: CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y PLL clock options: - More PLL source clocks: Existing: 1. HSE with: CONFIG_CLOCK_STM32_PLL_SRC_HSE=y New: 2. HSI with: CONFIG_CLOCK_STM32_PLL_SRC_HSI=y 3. CSI with: CONFIG_CLOCK_STM32_PLL_SRC_CSI=y - PLL vco input range is auto-calculated based on PLL DIVM1 -> Example for sysclock 96MHz generated with PLL from HSI CONFIG_CLOCK_STM32_PLL_SRC_HSI=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=96000000 CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y CONFIG_CLOCK_STM32_PLL_M_DIVISOR=4 CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=12 CONFIG_CLOCK_STM32_PLL_P_DIVISOR=2 CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=4 CONFIG_CLOCK_STM32_PLL_R_DIVISOR=2 Use LL_SetFlashLatency function from stm32h7xx_ll_utils.h instead to setup the correct latency. Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
2020-07-09 21:42:46 +02:00
#else
/* PLL will stay in reset state configuration */
drivers: clock_control: stm32h7: Use dts based configuration macros Update stm32h7 clock_control driver to make use of macros allowing dts based configuration in coexistance with existing Kconfig method. Note: Use of IS_ENABLED is removed as it generates warnings in checkpatch. This checkpatch behavior needs to be reviewed but may first require a little clean up of IS_ENABLED macro. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-04-29 14:41:58 +02:00
#endif /* STM32_PLL_SRC_* */
drivers: clock_control: stm32h7: Add HSE,HSI,CSI,PLL sysclk opt. Add HSE,HSI,CSI,PLL as system clock options. Also add correct configuration of the PLL. New sysclk options: - HSI with: CONFIG_CLOCK_STM32_SYSCLK_SRC_HSI=y - HSE with: CONFIG_CLOCK_STM32_SYSCLK_SRC_HSE=y - CSI with: CONFIG_CLOCK_STM32_SYSCLK_SRC_CSI=y Existing sysclk options: - PLL with: CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y PLL clock options: - More PLL source clocks: Existing: 1. HSE with: CONFIG_CLOCK_STM32_PLL_SRC_HSE=y New: 2. HSI with: CONFIG_CLOCK_STM32_PLL_SRC_HSI=y 3. CSI with: CONFIG_CLOCK_STM32_PLL_SRC_CSI=y - PLL vco input range is auto-calculated based on PLL DIVM1 -> Example for sysclock 96MHz generated with PLL from HSI CONFIG_CLOCK_STM32_PLL_SRC_HSI=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=96000000 CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y CONFIG_CLOCK_STM32_PLL_M_DIVISOR=4 CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=12 CONFIG_CLOCK_STM32_PLL_P_DIVISOR=2 CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=4 CONFIG_CLOCK_STM32_PLL_R_DIVISOR=2 Use LL_SetFlashLatency function from stm32h7xx_ll_utils.h instead to setup the correct latency. Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
2020-07-09 21:42:46 +02:00
drivers: clock_control: stm32h7 fix high frequency setting Fixes #27212 by setting the AHB/APBx dividers prior to configuring the PLL as clock source. Prevents going over the limits of APBx clocks when choosing the PLL as system clock source for high frequencies (close to 480MHz) Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
2020-07-28 21:13:23 +02:00
/* Preset the prescalers prior to chosing SYSCLK */
/* Prevents APB clock to go over limits */
/* Set buses (Sys,AHB, APB1, APB2 & APB4) prescalers */
drivers: clock_control: stm32h7: Use dts based configuration macros Update stm32h7 clock_control driver to make use of macros allowing dts based configuration in coexistance with existing Kconfig method. Note: Use of IS_ENABLED is removed as it generates warnings in checkpatch. This checkpatch behavior needs to be reviewed but may first require a little clean up of IS_ENABLED macro. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-04-29 14:41:58 +02:00
LL_RCC_SetSysPrescaler(sysclk_prescaler(STM32_D1CPRE));
LL_RCC_SetAHBPrescaler(ahb_prescaler(STM32_HPRE));
LL_RCC_SetAPB1Prescaler(apb1_prescaler(STM32_D2PPRE1));
LL_RCC_SetAPB2Prescaler(apb2_prescaler(STM32_D2PPRE2));
LL_RCC_SetAPB3Prescaler(apb3_prescaler(STM32_D1PPRE));
LL_RCC_SetAPB4Prescaler(apb4_prescaler(STM32_D3PPRE));
drivers: clock_control: stm32h7 fix high frequency setting Fixes #27212 by setting the AHB/APBx dividers prior to configuring the PLL as clock source. Prevents going over the limits of APBx clocks when choosing the PLL as system clock source for high frequencies (close to 480MHz) Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
2020-07-28 21:13:23 +02:00
drivers: clock_control: stm32h7: Use dts based configuration macros Update stm32h7 clock_control driver to make use of macros allowing dts based configuration in coexistance with existing Kconfig method. Note: Use of IS_ENABLED is removed as it generates warnings in checkpatch. This checkpatch behavior needs to be reviewed but may first require a little clean up of IS_ENABLED macro. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-04-29 14:41:58 +02:00
#if STM32_SYSCLK_SRC_PLL
drivers: clock_control: stm32h7: Add HSE,HSI,CSI,PLL sysclk opt. Add HSE,HSI,CSI,PLL as system clock options. Also add correct configuration of the PLL. New sysclk options: - HSI with: CONFIG_CLOCK_STM32_SYSCLK_SRC_HSI=y - HSE with: CONFIG_CLOCK_STM32_SYSCLK_SRC_HSE=y - CSI with: CONFIG_CLOCK_STM32_SYSCLK_SRC_CSI=y Existing sysclk options: - PLL with: CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y PLL clock options: - More PLL source clocks: Existing: 1. HSE with: CONFIG_CLOCK_STM32_PLL_SRC_HSE=y New: 2. HSI with: CONFIG_CLOCK_STM32_PLL_SRC_HSI=y 3. CSI with: CONFIG_CLOCK_STM32_PLL_SRC_CSI=y - PLL vco input range is auto-calculated based on PLL DIVM1 -> Example for sysclock 96MHz generated with PLL from HSI CONFIG_CLOCK_STM32_PLL_SRC_HSI=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=96000000 CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y CONFIG_CLOCK_STM32_PLL_M_DIVISOR=4 CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=12 CONFIG_CLOCK_STM32_PLL_P_DIVISOR=2 CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=4 CONFIG_CLOCK_STM32_PLL_R_DIVISOR=2 Use LL_SetFlashLatency function from stm32h7xx_ll_utils.h instead to setup the correct latency. Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
2020-07-09 21:42:46 +02:00
/* Enable PLL*/
drivers/clock_control: STM32H7 support Provide basic clock control driver for STM32H7. Bus clock activation is done through CM7 and CM4 common registers so we don't have to care to the CPU Id before accessing. Accesses are not protected for now. Only possible configuration is system clock source set to HSE driven PLL. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2019-07-01 14:12:48 +02:00
LL_RCC_PLL1_Enable();
while (LL_RCC_PLL1_IsReady() != 1) {
}
drivers: clock_control: stm32h7: Add HSE,HSI,CSI,PLL sysclk opt. Add HSE,HSI,CSI,PLL as system clock options. Also add correct configuration of the PLL. New sysclk options: - HSI with: CONFIG_CLOCK_STM32_SYSCLK_SRC_HSI=y - HSE with: CONFIG_CLOCK_STM32_SYSCLK_SRC_HSE=y - CSI with: CONFIG_CLOCK_STM32_SYSCLK_SRC_CSI=y Existing sysclk options: - PLL with: CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y PLL clock options: - More PLL source clocks: Existing: 1. HSE with: CONFIG_CLOCK_STM32_PLL_SRC_HSE=y New: 2. HSI with: CONFIG_CLOCK_STM32_PLL_SRC_HSI=y 3. CSI with: CONFIG_CLOCK_STM32_PLL_SRC_CSI=y - PLL vco input range is auto-calculated based on PLL DIVM1 -> Example for sysclock 96MHz generated with PLL from HSI CONFIG_CLOCK_STM32_PLL_SRC_HSI=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=96000000 CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y CONFIG_CLOCK_STM32_PLL_M_DIVISOR=4 CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=12 CONFIG_CLOCK_STM32_PLL_P_DIVISOR=2 CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=4 CONFIG_CLOCK_STM32_PLL_R_DIVISOR=2 Use LL_SetFlashLatency function from stm32h7xx_ll_utils.h instead to setup the correct latency. Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
2020-07-09 21:42:46 +02:00
/* Set PLL1 as System Clock Source */
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL1);
while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL1) {
}
drivers: clock_control: stm32h7: Use dts based configuration macros Update stm32h7 clock_control driver to make use of macros allowing dts based configuration in coexistance with existing Kconfig method. Note: Use of IS_ENABLED is removed as it generates warnings in checkpatch. This checkpatch behavior needs to be reviewed but may first require a little clean up of IS_ENABLED macro. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-04-29 14:41:58 +02:00
#elif STM32_SYSCLK_SRC_HSE
drivers: clock_control: stm32h7: Add HSE,HSI,CSI,PLL sysclk opt. Add HSE,HSI,CSI,PLL as system clock options. Also add correct configuration of the PLL. New sysclk options: - HSI with: CONFIG_CLOCK_STM32_SYSCLK_SRC_HSI=y - HSE with: CONFIG_CLOCK_STM32_SYSCLK_SRC_HSE=y - CSI with: CONFIG_CLOCK_STM32_SYSCLK_SRC_CSI=y Existing sysclk options: - PLL with: CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y PLL clock options: - More PLL source clocks: Existing: 1. HSE with: CONFIG_CLOCK_STM32_PLL_SRC_HSE=y New: 2. HSI with: CONFIG_CLOCK_STM32_PLL_SRC_HSI=y 3. CSI with: CONFIG_CLOCK_STM32_PLL_SRC_CSI=y - PLL vco input range is auto-calculated based on PLL DIVM1 -> Example for sysclock 96MHz generated with PLL from HSI CONFIG_CLOCK_STM32_PLL_SRC_HSI=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=96000000 CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y CONFIG_CLOCK_STM32_PLL_M_DIVISOR=4 CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=12 CONFIG_CLOCK_STM32_PLL_P_DIVISOR=2 CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=4 CONFIG_CLOCK_STM32_PLL_R_DIVISOR=2 Use LL_SetFlashLatency function from stm32h7xx_ll_utils.h instead to setup the correct latency. Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
2020-07-09 21:42:46 +02:00
/* Enable HSI oscillator */
LL_RCC_HSE_Enable();
while (LL_RCC_HSE_IsReady() != 1) {
}
/* Set sysclk source to HSE */
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSE);
while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSE) {
}
drivers: clock_control: stm32h7: Use dts based configuration macros Update stm32h7 clock_control driver to make use of macros allowing dts based configuration in coexistance with existing Kconfig method. Note: Use of IS_ENABLED is removed as it generates warnings in checkpatch. This checkpatch behavior needs to be reviewed but may first require a little clean up of IS_ENABLED macro. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-04-29 14:41:58 +02:00
#elif STM32_SYSCLK_SRC_HSI
drivers: clock_control: stm32h7: Add HSE,HSI,CSI,PLL sysclk opt. Add HSE,HSI,CSI,PLL as system clock options. Also add correct configuration of the PLL. New sysclk options: - HSI with: CONFIG_CLOCK_STM32_SYSCLK_SRC_HSI=y - HSE with: CONFIG_CLOCK_STM32_SYSCLK_SRC_HSE=y - CSI with: CONFIG_CLOCK_STM32_SYSCLK_SRC_CSI=y Existing sysclk options: - PLL with: CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y PLL clock options: - More PLL source clocks: Existing: 1. HSE with: CONFIG_CLOCK_STM32_PLL_SRC_HSE=y New: 2. HSI with: CONFIG_CLOCK_STM32_PLL_SRC_HSI=y 3. CSI with: CONFIG_CLOCK_STM32_PLL_SRC_CSI=y - PLL vco input range is auto-calculated based on PLL DIVM1 -> Example for sysclock 96MHz generated with PLL from HSI CONFIG_CLOCK_STM32_PLL_SRC_HSI=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=96000000 CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y CONFIG_CLOCK_STM32_PLL_M_DIVISOR=4 CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=12 CONFIG_CLOCK_STM32_PLL_P_DIVISOR=2 CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=4 CONFIG_CLOCK_STM32_PLL_R_DIVISOR=2 Use LL_SetFlashLatency function from stm32h7xx_ll_utils.h instead to setup the correct latency. Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
2020-07-09 21:42:46 +02:00
/* Enable HSI oscillator */
LL_RCC_HSI_Enable();
while (LL_RCC_HSI_IsReady() != 1) {
}
drivers: clock_control: stm32h7 add HSI divisor support Add HSI divisor support for clock tree configuration. Removed HSI calibration trimming to comply with common STM32 implementation and use reset default configuration instead. Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
2020-07-30 09:45:32 +02:00
/* HSI divider configuration */
drivers: clock_control: stm32h7: Use dts based configuration macros Update stm32h7 clock_control driver to make use of macros allowing dts based configuration in coexistance with existing Kconfig method. Note: Use of IS_ENABLED is removed as it generates warnings in checkpatch. This checkpatch behavior needs to be reviewed but may first require a little clean up of IS_ENABLED macro. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-04-29 14:41:58 +02:00
LL_RCC_HSI_SetDivider(hsi_divider(STM32_HSI_DIVISOR));
drivers: clock_control: stm32h7 add HSI divisor support Add HSI divisor support for clock tree configuration. Removed HSI calibration trimming to comply with common STM32 implementation and use reset default configuration instead. Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
2020-07-30 09:45:32 +02:00
drivers: clock_control: stm32h7: Add HSE,HSI,CSI,PLL sysclk opt. Add HSE,HSI,CSI,PLL as system clock options. Also add correct configuration of the PLL. New sysclk options: - HSI with: CONFIG_CLOCK_STM32_SYSCLK_SRC_HSI=y - HSE with: CONFIG_CLOCK_STM32_SYSCLK_SRC_HSE=y - CSI with: CONFIG_CLOCK_STM32_SYSCLK_SRC_CSI=y Existing sysclk options: - PLL with: CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y PLL clock options: - More PLL source clocks: Existing: 1. HSE with: CONFIG_CLOCK_STM32_PLL_SRC_HSE=y New: 2. HSI with: CONFIG_CLOCK_STM32_PLL_SRC_HSI=y 3. CSI with: CONFIG_CLOCK_STM32_PLL_SRC_CSI=y - PLL vco input range is auto-calculated based on PLL DIVM1 -> Example for sysclock 96MHz generated with PLL from HSI CONFIG_CLOCK_STM32_PLL_SRC_HSI=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=96000000 CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y CONFIG_CLOCK_STM32_PLL_M_DIVISOR=4 CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=12 CONFIG_CLOCK_STM32_PLL_P_DIVISOR=2 CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=4 CONFIG_CLOCK_STM32_PLL_R_DIVISOR=2 Use LL_SetFlashLatency function from stm32h7xx_ll_utils.h instead to setup the correct latency. Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
2020-07-09 21:42:46 +02:00
/* Set sysclk source to HSI */
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSI);
while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI) {
}
drivers: clock_control: stm32h7: Use dts based configuration macros Update stm32h7 clock_control driver to make use of macros allowing dts based configuration in coexistance with existing Kconfig method. Note: Use of IS_ENABLED is removed as it generates warnings in checkpatch. This checkpatch behavior needs to be reviewed but may first require a little clean up of IS_ENABLED macro. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-04-29 14:41:58 +02:00
#elif STM32_SYSCLK_SRC_CSI
drivers: clock_control: stm32h7: Add HSE,HSI,CSI,PLL sysclk opt. Add HSE,HSI,CSI,PLL as system clock options. Also add correct configuration of the PLL. New sysclk options: - HSI with: CONFIG_CLOCK_STM32_SYSCLK_SRC_HSI=y - HSE with: CONFIG_CLOCK_STM32_SYSCLK_SRC_HSE=y - CSI with: CONFIG_CLOCK_STM32_SYSCLK_SRC_CSI=y Existing sysclk options: - PLL with: CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y PLL clock options: - More PLL source clocks: Existing: 1. HSE with: CONFIG_CLOCK_STM32_PLL_SRC_HSE=y New: 2. HSI with: CONFIG_CLOCK_STM32_PLL_SRC_HSI=y 3. CSI with: CONFIG_CLOCK_STM32_PLL_SRC_CSI=y - PLL vco input range is auto-calculated based on PLL DIVM1 -> Example for sysclock 96MHz generated with PLL from HSI CONFIG_CLOCK_STM32_PLL_SRC_HSI=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=96000000 CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y CONFIG_CLOCK_STM32_PLL_M_DIVISOR=4 CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=12 CONFIG_CLOCK_STM32_PLL_P_DIVISOR=2 CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=4 CONFIG_CLOCK_STM32_PLL_R_DIVISOR=2 Use LL_SetFlashLatency function from stm32h7xx_ll_utils.h instead to setup the correct latency. Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
2020-07-09 21:42:46 +02:00
/* Enable CSI oscillator */
LL_RCC_CSI_Enable();
while (LL_RCC_CSI_IsReady() != 1) {
}
/* Set sysclk source to CSI */
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_CSI);
while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_CSI) {
}
drivers: clock_control: stm32h7: Use dts based configuration macros Update stm32h7 clock_control driver to make use of macros allowing dts based configuration in coexistance with existing Kconfig method. Note: Use of IS_ENABLED is removed as it generates warnings in checkpatch. This checkpatch behavior needs to be reviewed but may first require a little clean up of IS_ENABLED macro. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-04-29 14:41:58 +02:00
#endif /* STM32_SYSCLK_SRC */
drivers: clock_control: stm32h7: Add HSE,HSI,CSI,PLL sysclk opt. Add HSE,HSI,CSI,PLL as system clock options. Also add correct configuration of the PLL. New sysclk options: - HSI with: CONFIG_CLOCK_STM32_SYSCLK_SRC_HSI=y - HSE with: CONFIG_CLOCK_STM32_SYSCLK_SRC_HSE=y - CSI with: CONFIG_CLOCK_STM32_SYSCLK_SRC_CSI=y Existing sysclk options: - PLL with: CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y PLL clock options: - More PLL source clocks: Existing: 1. HSE with: CONFIG_CLOCK_STM32_PLL_SRC_HSE=y New: 2. HSI with: CONFIG_CLOCK_STM32_PLL_SRC_HSI=y 3. CSI with: CONFIG_CLOCK_STM32_PLL_SRC_CSI=y - PLL vco input range is auto-calculated based on PLL DIVM1 -> Example for sysclock 96MHz generated with PLL from HSI CONFIG_CLOCK_STM32_PLL_SRC_HSI=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=96000000 CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y CONFIG_CLOCK_STM32_PLL_M_DIVISOR=4 CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=12 CONFIG_CLOCK_STM32_PLL_P_DIVISOR=2 CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=4 CONFIG_CLOCK_STM32_PLL_R_DIVISOR=2 Use LL_SetFlashLatency function from stm32h7xx_ll_utils.h instead to setup the correct latency. Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
2020-07-09 21:42:46 +02:00
/* Set FLASH latency */
drivers: clock_control: stm32h7 change set flash latency Updated flash latency setting to comply with common stm32 implementation and datasheet. Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
2020-07-29 20:34:46 +02:00
/* AHB/AXI/HCLK clock is SYSCLK / HPRE */
/* If freq not increased, set flash latency after all clock setting */
if (new_hclk_freq <= old_hclk_freq) {
LL_SetFlashLatency(new_hclk_freq);
}
drivers: STM32 dualcore concurrent register access protection with HSEM In case of dualcore, STM32H7, STM32W and STM32MP1, protect concurrent register write access with HSEM. Done for following drivers: clock_control, counter, flash, gpio, interrupt_controller Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
2020-06-23 09:48:07 +02:00
drivers: clock_control: stm32h7: Add HSE,HSI,CSI,PLL sysclk opt. Add HSE,HSI,CSI,PLL as system clock options. Also add correct configuration of the PLL. New sysclk options: - HSI with: CONFIG_CLOCK_STM32_SYSCLK_SRC_HSI=y - HSE with: CONFIG_CLOCK_STM32_SYSCLK_SRC_HSE=y - CSI with: CONFIG_CLOCK_STM32_SYSCLK_SRC_CSI=y Existing sysclk options: - PLL with: CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y PLL clock options: - More PLL source clocks: Existing: 1. HSE with: CONFIG_CLOCK_STM32_PLL_SRC_HSE=y New: 2. HSI with: CONFIG_CLOCK_STM32_PLL_SRC_HSI=y 3. CSI with: CONFIG_CLOCK_STM32_PLL_SRC_CSI=y - PLL vco input range is auto-calculated based on PLL DIVM1 -> Example for sysclock 96MHz generated with PLL from HSI CONFIG_CLOCK_STM32_PLL_SRC_HSI=y CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=96000000 CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y CONFIG_CLOCK_STM32_PLL_M_DIVISOR=4 CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=12 CONFIG_CLOCK_STM32_PLL_P_DIVISOR=2 CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=4 CONFIG_CLOCK_STM32_PLL_R_DIVISOR=2 Use LL_SetFlashLatency function from stm32h7xx_ll_utils.h instead to setup the correct latency. Signed-off-by: Jeremy LOCHE <lochejeremy@gmail.com>
2020-07-09 21:42:46 +02:00
optimize_regulator_voltage_scale(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC);
z_stm32_hsem_unlock(CFG_HW_RCC_SEMID);
drivers/clock_control: STM32H7 support Provide basic clock control driver for STM32H7. Bus clock activation is done through CM7 and CM4 common registers so we don't have to care to the CPU Id before accessing. Accesses are not protected for now. Only possible configuration is system clock source set to HSE driven PLL. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2019-07-01 14:12:48 +02:00
drivers/clock_control: stm32h7: Disable configuration for CM4 core On STM32H7, in Dual core configuration, we restrict configuration access to CM7 core. CM4 can access to API but not the init part of the driver. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2019-06-14 16:18:39 +02:00
#endif /* CONFIG_CPU_CORTEX_M4 */
drivers: clock_control: stm32h7: Use dts based configuration macros Update stm32h7 clock_control driver to make use of macros allowing dts based configuration in coexistance with existing Kconfig method. Note: Use of IS_ENABLED is removed as it generates warnings in checkpatch. This checkpatch behavior needs to be reviewed but may first require a little clean up of IS_ENABLED macro. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-04-29 14:41:58 +02:00
#if STM32_PLL3_ENABLE
drivers: clock_control: add support for PLL3 on STM32 H7 Add support for enabling and configuring PLL3 on STM32 H7 series. PLL3 is used as a clock source by certain peripherals, e.g. LTDC. Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2020-12-19 11:24:43 +01:00
/* Initialize PLL 3 */
drivers: clock_control: stm32h7: Use dts based configuration macros Update stm32h7 clock_control driver to make use of macros allowing dts based configuration in coexistance with existing Kconfig method. Note: Use of IS_ENABLED is removed as it generates warnings in checkpatch. This checkpatch behavior needs to be reviewed but may first require a little clean up of IS_ENABLED macro. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-04-29 14:41:58 +02:00
r = get_vco_input_range(STM32_PLL3_M_DIVISOR, &vco_input_range);
drivers: clock_control: add support for PLL3 on STM32 H7 Add support for enabling and configuring PLL3 on STM32 H7 series. PLL3 is used as a clock source by certain peripherals, e.g. LTDC. Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2020-12-19 11:24:43 +01:00
if (r < 0) {
return r;
}
vco_output_range = get_vco_output_range(vco_input_range);
LL_RCC_PLL3FRACN_Disable();
drivers: clock_control: stm32h7: Use dts based configuration macros Update stm32h7 clock_control driver to make use of macros allowing dts based configuration in coexistance with existing Kconfig method. Note: Use of IS_ENABLED is removed as it generates warnings in checkpatch. This checkpatch behavior needs to be reviewed but may first require a little clean up of IS_ENABLED macro. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-04-29 14:41:58 +02:00
LL_RCC_PLL3_SetM(STM32_PLL3_M_DIVISOR);
LL_RCC_PLL3_SetN(STM32_PLL3_N_MULTIPLIER);
drivers: clock_control: add support for PLL3 on STM32 H7 Add support for enabling and configuring PLL3 on STM32 H7 series. PLL3 is used as a clock source by certain peripherals, e.g. LTDC. Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2020-12-19 11:24:43 +01:00
LL_RCC_PLL3_SetVCOInputRange(vco_input_range);
LL_RCC_PLL3_SetVCOOutputRange(vco_output_range);
drivers: clock_control: stm32h7: Use dts based configuration macros Update stm32h7 clock_control driver to make use of macros allowing dts based configuration in coexistance with existing Kconfig method. Note: Use of IS_ENABLED is removed as it generates warnings in checkpatch. This checkpatch behavior needs to be reviewed but may first require a little clean up of IS_ENABLED macro. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-04-29 14:41:58 +02:00
#if STM32_PLL3_P_ENABLE
drivers: clock_control: add support for PLL3 on STM32 H7 Add support for enabling and configuring PLL3 on STM32 H7 series. PLL3 is used as a clock source by certain peripherals, e.g. LTDC. Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2020-12-19 11:24:43 +01:00
LL_RCC_PLL3P_Enable();
drivers: clock_control: stm32h7: Use dts based configuration macros Update stm32h7 clock_control driver to make use of macros allowing dts based configuration in coexistance with existing Kconfig method. Note: Use of IS_ENABLED is removed as it generates warnings in checkpatch. This checkpatch behavior needs to be reviewed but may first require a little clean up of IS_ENABLED macro. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-04-29 14:41:58 +02:00
LL_RCC_PLL3_SetP(STM32_PLL3_P_DIVISOR);
#endif /* STM32_PLL3_P_ENABLE */
#if STM32_PLL3_Q_ENABLE
drivers: clock_control: add support for PLL3 on STM32 H7 Add support for enabling and configuring PLL3 on STM32 H7 series. PLL3 is used as a clock source by certain peripherals, e.g. LTDC. Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2020-12-19 11:24:43 +01:00
LL_RCC_PLL3Q_Enable();
drivers: clock_control: stm32h7: Use dts based configuration macros Update stm32h7 clock_control driver to make use of macros allowing dts based configuration in coexistance with existing Kconfig method. Note: Use of IS_ENABLED is removed as it generates warnings in checkpatch. This checkpatch behavior needs to be reviewed but may first require a little clean up of IS_ENABLED macro. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-04-29 14:41:58 +02:00
LL_RCC_PLL3_SetQ(STM32_PLL3_Q_DIVISOR);
#endif /* STM32_PLL3_Q_ENABLE */
#if STM32_PLL3_R_ENABLE
drivers: clock_control: add support for PLL3 on STM32 H7 Add support for enabling and configuring PLL3 on STM32 H7 series. PLL3 is used as a clock source by certain peripherals, e.g. LTDC. Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2020-12-19 11:24:43 +01:00
LL_RCC_PLL3R_Enable();
drivers: clock_control: stm32h7: Use dts based configuration macros Update stm32h7 clock_control driver to make use of macros allowing dts based configuration in coexistance with existing Kconfig method. Note: Use of IS_ENABLED is removed as it generates warnings in checkpatch. This checkpatch behavior needs to be reviewed but may first require a little clean up of IS_ENABLED macro. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-04-29 14:41:58 +02:00
LL_RCC_PLL3_SetR(STM32_PLL3_R_DIVISOR);
#endif /* STM32_PLL3_R_ENABLE */
drivers: clock_control: add support for PLL3 on STM32 H7 Add support for enabling and configuring PLL3 on STM32 H7 series. PLL3 is used as a clock source by certain peripherals, e.g. LTDC. Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2020-12-19 11:24:43 +01:00
LL_RCC_PLL3_Enable();
while (LL_RCC_PLL3_IsReady() != 1U) {
}
drivers: clock_control: stm32h7: Use dts based configuration macros Update stm32h7 clock_control driver to make use of macros allowing dts based configuration in coexistance with existing Kconfig method. Note: Use of IS_ENABLED is removed as it generates warnings in checkpatch. This checkpatch behavior needs to be reviewed but may first require a little clean up of IS_ENABLED macro. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2021-04-29 14:41:58 +02:00
#endif /* STM32_PLL3_ENABLE */
drivers: clock_control: add support for PLL3 on STM32 H7 Add support for enabling and configuring PLL3 on STM32 H7 series. PLL3 is used as a clock source by certain peripherals, e.g. LTDC. Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2020-12-19 11:24:43 +01:00
drivers/clock_control: STM32H7 support Provide basic clock control driver for STM32H7. Bus clock activation is done through CM7 and CM4 common registers so we don't have to care to the CPU Id before accessing. Accesses are not protected for now. Only possible configuration is system clock source set to HSE driven PLL. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2019-07-01 14:12:48 +02:00
/* Set systick to 1ms */
SysTick_Config(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC / 1000);
/* Update CMSIS variable */
SystemCoreClock = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC;
return 0;
}
/**
* @brief RCC device, note that priority is intentionally set to 1 so
* that the device init runs just after SOC init
*/
drivers: clock_control: stm32: Convert drivers to new DT device macros Convert clock_control drivers from: DEVICE_AND_API_INIT -> DEVICE_DT_DEFINE As part of this we also changed STM32_CLOCK_CONTROL_NAME to be based on devicetree. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-12-15 19:32:21 +01:00
DEVICE_DT_DEFINE(DT_NODELABEL(rcc),
drivers/clock_control: STM32H7 support Provide basic clock control driver for STM32H7. Bus clock activation is done through CM7 and CM4 common registers so we don't have to care to the CPU Id before accessing. Accesses are not protected for now. Only possible configuration is system clock source set to HSE driven PLL. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2019-07-01 14:12:48 +02:00
&stm32_clock_control_init,
drivers: clock_control: remove usage of device_pm_control_nop device_pm_control_nop is now deprecated in favour of NULL. Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2021-04-28 10:19:07 +02:00
NULL,
drivers/clock_control: STM32H7 support Provide basic clock control driver for STM32H7. Bus clock activation is done through CM7 and CM4 common registers so we don't have to care to the CPU Id before accessing. Accesses are not protected for now. Only possible configuration is system clock source set to HSE driven PLL. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2019-07-01 14:12:48 +02:00
NULL, NULL,
PRE_KERNEL_1,
drivers: clock_control: Refactor drivers to use shared init priority Refactors all of the clock control drivers to use a shared driver class initialization priority configuration, CONFIG_CLOCK_CONTROL_INIT_PRIORITY, to allow configuring clock control drivers separately from other devices. This is similar to other driver classes like I2C and SPI. Most drivers previously used CONFIG_KERNEL_INIT_PRIORITY_OBJECTS or CONFIG_KERNEL_INIT_PRIORITY_DEVICE, therefore the default for this new option is the lower of the two, which means earlier initialization. The even lower defaults for STM32 and Arm Beetle are preserved by SoC-family level overrides. Signed-off-by: Maureen Helm <maureen.helm@intel.com>
2021-10-18 21:45:17 +02:00
CONFIG_CLOCK_CONTROL_INIT_PRIORITY,
drivers/clock_control: STM32H7 support Provide basic clock control driver for STM32H7. Bus clock activation is done through CM7 and CM4 common registers so we don't have to care to the CPU Id before accessing. Accesses are not protected for now. Only possible configuration is system clock source set to HSE driven PLL. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2019-07-01 14:12:48 +02:00
&stm32_clock_control_api);
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