27 lines
899 B
Plaintext
27 lines
899 B
Plaintext
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# Copyright (c) 2014-2015 Wind River Systems, Inc.
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# Copyright (c) 2016 Cadence Design Systems, Inc.
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# Copyright (c) 2019 Intel Corp.
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# SPDX-License-Identifier: Apache-2.0
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config XTENSA_TIMER
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bool "Xtensa timer support"
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depends on XTENSA
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default y
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select TICKLESS_CAPABLE
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help
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Enables a system timer driver for Xtensa based on the CCOUNT
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and CCOMPARE special registers.
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config XTENSA_TIMER_ID
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int "System timer CCOMPAREn register index"
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default 1
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depends on XTENSA_TIMER
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help
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Index of the CCOMPARE register (and associated interrupt)
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used for the system timer. Xtensa CPUs have hard-configured
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interrupt priorities associated with each timer, and some of
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them can be unmaskable (and thus not usable by OS code that
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need synchronization, like the timer subsystem!). Choose
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carefully. Generally you want the timer with the highest
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priority maskable interrupt.
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