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zephyr/drivers/interrupt_controller/CMakeLists.txt

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license: cleanup: add SPDX Apache-2.0 license identifier Update the files which contain no license information with the 'Apache-2.0' SPDX license identifier. Many source files in the tree are missing licensing information, which makes it harder for compliance tools to determine the correct license. By default all files without license information are under the default license of Zephyr, which is Apache version 2. Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2019-04-06 15:08:09 +02:00
# SPDX-License-Identifier: Apache-2.0
drivers: interrupt_controller: build as static library Instead of putting object files inside libzephyr.a, simply build a separate static library as most other driver types are doing this already. Also sort the entries alphabetically. Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2021-08-04 20:54:40 +02:00
zephyr_library()
drives: cmake: zephyr_library_property(ALLOW_EMPTY TRUE) on drivers lib This commit now sets the Zephyr library property `ALLOW_EMPTY` to silence the warning: `No SOURCES given to Zephyr library: drivers__interrupt_controller` Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
2021-09-06 16:54:03 +02:00
zephyr_library_property(ALLOW_EMPTY TRUE)
drivers: interrupt_controller: build as static library Instead of putting object files inside libzephyr.a, simply build a separate static library as most other driver types are doing this already. Also sort the entries alphabetically. Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2021-08-04 20:54:40 +02:00
zephyr_library_sources_ifdef(CONFIG_ARCV2_INTERRUPT_UNIT intc_arcv2_irq_unit.c)
zephyr_library_sources_ifdef(CONFIG_CAVS_ICTL intc_cavs.c)
zephyr_library_sources_ifdef(CONFIG_DW_ICTL intc_dw.c)
drivers: intc_dw_ace: use CONFIG_DW_ICTL_ACE Use CONFIG_DW_ICTL_ACE instead of a version kconfig. Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2022-10-03 19:55:37 +02:00
zephyr_library_sources_ifdef(CONFIG_DW_ICTL_ACE intc_dw_ace.c)
drivers: interrupt_controller: build as static library Instead of putting object files inside libzephyr.a, simply build a separate static library as most other driver types are doing this already. Also sort the entries alphabetically. Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2021-08-04 20:54:40 +02:00
zephyr_library_sources_ifdef(CONFIG_EXTI_STM32 intc_exti_stm32.c)
drivers: interrupt_controller: initial support for GD32 EXTI Add initial support for the GigaDevice External Interrupt Controller. This driver is required to manage GPIO interrupts. Only EXTI lines 0 to 15 are supported for now (no LVD, RTC, etc.). Driver can be extended in the future to add support for extra EXTI lines. Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2021-12-07 18:59:00 +01:00
zephyr_library_sources_ifdef(CONFIG_GD32_EXTI intc_gd32_exti.c)
drivers: interrupt_controller: build as static library Instead of putting object files inside libzephyr.a, simply build a separate static library as most other driver types are doing this already. Also sort the entries alphabetically. Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2021-08-04 20:54:40 +02:00
zephyr_library_sources_ifdef(CONFIG_GIC_V1 intc_gic.c)
zephyr_library_sources_ifdef(CONFIG_GIC_V2 intc_gic.c)
zephyr_library_sources_ifdef(CONFIG_GIC_V3 intc_gicv3.c)
interrupt_controller: gicv3: add Interrupt Translation Service support This implements support for the optional Interrupt Translation Service (ITS) module of the GICv3 Interrupt Controller. The current implementation is designed for MSI/MSI-X interrupt delivery in mind. The gicv3 driver calls each ITS INVALL command when LPI interrupts are enabled/disabled. A simple atomic integer is used to allocate unique LPI INTIDs to ITS users. CPUs numbers are directly mapped as ICIDs into the Collections Table. As a limitation it doesn't support indirect Device table to simplify implementation but may use a large amount of memory. INV, DISCARD, MOVI and MOVALL commands are not implemented. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-08-06 16:32:53 +02:00
zephyr_library_sources_ifdef(CONFIG_GIC_V3_ITS intc_gicv3_its.c)
drivers: interrupt_controller: build as static library Instead of putting object files inside libzephyr.a, simply build a separate static library as most other driver types are doing this already. Also sort the entries alphabetically. Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2021-08-04 20:54:40 +02:00
zephyr_library_sources_ifdef(CONFIG_INTEL_VTD_ICTL intc_intel_vtd.c)
zephyr_library_sources_ifdef(CONFIG_IOAPIC intc_ioapic.c)
zephyr_library_sources_ifdef(CONFIG_ITE_IT8XXX2_INTC intc_ite_it8xxx2.c)
ITE drivers/interrupt_controller: add intc_ite_it8xxx2_v2 driver This driver is made for it82xx2 series. Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
2022-10-05 08:05:43 +02:00
zephyr_library_sources_ifdef(CONFIG_ITE_IT8XXX2_INTC_V2 intc_ite_it8xxx2_v2.c)
ITE drivers/interrupt_controller: add wuc interface Add wakeup controller interface for ITE it8xxx2 chip. Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
2021-09-07 07:45:39 +02:00
zephyr_library_sources_ifdef(CONFIG_ITE_IT8XXX2_WUC wuc_ite_it8xxx2.c)
drivers: interrupt_controller: build as static library Instead of putting object files inside libzephyr.a, simply build a separate static library as most other driver types are doing this already. Also sort the entries alphabetically. Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2021-08-04 20:54:40 +02:00
zephyr_library_sources_ifdef(CONFIG_LEON_IRQMP intc_irqmp.c)
zephyr_library_sources_ifdef(CONFIG_LOAPIC intc_loapic.c intc_system_apic.c)
zephyr_library_sources_ifdef(CONFIG_LOAPIC_SPURIOUS_VECTOR intc_loapic_spurious.S)
zephyr_library_sources_ifdef(CONFIG_MCHP_ECIA_XEC intc_mchp_ecia_xec.c)
zephyr_library_sources_ifdef(CONFIG_NPCX_MIWU intc_miwu.c)
zephyr_library_sources_ifdef(CONFIG_PLIC intc_plic.c)
zephyr_library_sources_ifdef(CONFIG_RV32M1_INTMUX intc_rv32m1_intmux.c)
zephyr_library_sources_ifdef(CONFIG_SAM0_EIC intc_sam0_eic.c)
zephyr_library_sources_ifdef(CONFIG_SHARED_IRQ intc_shared_irq.c)
esp32: drivers: interrupt_controller: make it common for xtensa socs by including interrupt allocation feature whenever an Xtensa-based Espressif SoC is selected. Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
2021-08-21 01:12:07 +02:00
zephyr_library_sources_ifdef(CONFIG_INTC_ESP32 intc_esp32.c)
interrupt_controller: intc_esp32c3: added intc driver For esp32c3 and replaces the hardcoded interrupt attaching procedures with this new driver. Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
2021-08-30 15:04:34 +02:00
zephyr_library_sources_ifdef(CONFIG_INTC_ESP32C3 intc_esp32c3.c)
drivers: interrupt_controller: build as static library Instead of putting object files inside libzephyr.a, simply build a separate static library as most other driver types are doing this already. Also sort the entries alphabetically. Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2021-08-04 20:54:40 +02:00
zephyr_library_sources_ifdef(CONFIG_SWERV_PIC intc_swerv_pic.c)
zephyr_library_sources_ifdef(CONFIG_VEXRISCV_LITEX_IRQ intc_vexriscv_litex.c)
drivers: interrupt-controller: Add VIM Interrupt Controller support Add TI VIM (Vectored Interrupt Manager) interrupt controller support. VIM is a TI specific custom interrupt controller for ARM cores. In J721E soc, VIM aggregates interrupts to Cortex R5 cores. TRM for J721e https://www.ti.com/lit/zip/spruil1 File: spruil1c.pdf VIM: section 6.3.3.6 Signed-off-by: Prashanth S <slpp95prashanth@yahoo.com>
2023-06-27 15:26:50 +02:00
zephyr_library_sources_ifdef(CONFIG_VIM intc_vim.c)
drivers: interrupt-controller: add Nuclei ECLIC driver Add support for the ECLIC interrupt controller which is used with the Nuclei processor core. Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
2021-11-15 00:34:11 +01:00
zephyr_library_sources_ifdef(CONFIG_NUCLEI_ECLIC intc_nuclei_eclic.c)
riscv: irq: Correct interrupt handling in clic non-vectored mode According to the clic specification (https://github.com/riscv/riscv-fast-interrupt), the mnxti register has be written, in order to clear the pending bit for non-vectored interrupts. For vectored interrupts, this is automatically done. From the spec: "If the pending interrupt is edge-triggered, hardware will automatically clear the corresponding pending bit when the CSR instruction that accesses xnxti includes a write." I added a kconfig `RISCV_SOC_HAS_CUSTOM_IRQ_HANDLING` to allow custom irq handling. If enabled, `__soc_handle_all_irqs` has to be implemented. For clic, non-vectored mode, I added a `__soc_handle_all_irqs`, that handles the pending interrupts according to the pseudo code in the spec. Signed-off-by: Greter Raffael <rgreter@baumer.com>
2023-12-21 13:41:59 +01:00
zephyr_library_sources_ifdef(CONFIG_NUCLEI_ECLIC intc_nuclei_eclic.S)
drivers: interrupt_controller: add intc_nrfx_clic Add interrupt controller driver for Nordic Semiconductor VPR CLIC. Signed-off-by: Marcin Szymczyk <marcin.szymczyk@nordicsemi.no>
2024-04-04 11:08:44 +02:00
zephyr_library_sources_ifdef(CONFIG_NRFX_CLIC intc_nrfx_clic.c)
zephyr_library_sources_ifdef(CONFIG_NRFX_CLIC intc_nrfx_clic.S)
drivers: interrupt_controller: initial support for NXP S32Z27 EIRQ Add initial support for the NXP S32Z27 SIUL2 External Interrupt Controller. Each SIUL2 node has a child node will act as an interrupt-controller that processes external interrupt signals. This driver is required to manage GPIO interrupts. Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
2022-10-12 09:37:52 +02:00
zephyr_library_sources_ifdef(CONFIG_NXP_S32_EIRQ intc_eirq_nxp_s32.c)
intc: add NXP S32 WKPU interrupt controller driver Introduce an interrupt controller for the NXP S32 WKPU peripheral that can be integrated with GPIO to trigger interrupts through external interrupt pad inputs. WKPU can trigger interrupts from certain input pads that support this function, as well as wake-up events to the power management domain. This patch only adds WKPU functionality as an interrupt controller to extend the number of input pads that can interrupt the core. Power management functionalities are not supported. Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2023-09-11 08:35:59 +02:00
zephyr_library_sources_ifdef(CONFIG_NXP_S32_WKPU intc_wkpu_nxp_s32.c)
drivers: interrupt_controller: Add XMC4XXX ERU driver In Infineon XMC4XXX SoCs, gpio interrupts are triggered via an Event Request Unit (ERU) module. A subset of the gpios are connected to the ERU. The ERU monitors edge triggers and creates a SR. This driver configures the ERU for a target port/pin combination for rising/falling edge events. Note that the ERU module does not generate SR based on the gpio level. Internally the ERU tracks the *status* of an event. The status is set on a positive edge and unset on a negative edge (or vice-versa depending on the configuration). The value of the status is used to implement a level triggered interrupt; The ISR checks the status flag and calls the callback function if the status is set. The ERU configurations for supported port/pin combinations are stored in a devicetree file dts/arm/infineon/xmc4xxx_x_x-intc.dtsi. The configurations are stored in the opaque array uint16 port_line_mapping[]. Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
2022-07-21 20:33:28 +02:00
zephyr_library_sources_ifdef(CONFIG_XMC4XXX_INTC intc_xmc4xxx.c)
drivers: interrupt_controller: introduce PINT driver Introduce PINT driver, for NXP pin interrupt and pattern match engine. The driver currently supports only the pin interrupt feature of the PINT. Add DTS entires for the PINT on LPC and RT devices that support this peripheral, and remove the interrupt defintions that are PINT specific from the GPIO module on these devices. Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2023-04-10 23:30:23 +02:00
zephyr_library_sources_ifdef(CONFIG_NXP_PINT intc_nxp_pint.c)
drivers: intc: Rename renesas ra driver Need this rename to be able to target this driver in the "Renesas RA" maintainer area. Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
2024-01-24 16:06:24 +01:00
zephyr_library_sources_ifdef(CONFIG_RENESAS_RA_ICU intc_renesas_ra_icu.c)
drivers: interrupt_controller: Add driver for NXP's IRQ_STEER IP This commit introduces a new interrupt controller driver used for NXP's IRQ_STEER IP. Apart from introducing the driver itself, this commit contains the following changes: 1) Switch i.MX8MP to using the XTENSA core interrupt controller instead of the dummy irqsteer one. * this is required because the binding for the irqsteer driver is no longer a dummy one (since it's being used by the irqsteer driver). As such, to avoid having problems, switch to using another dummy binding. 2) Modify the irqsteer dummy binding such that it serves the IRQ_STEER driver's needs. Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
2023-09-18 15:09:58 +02:00
zephyr_library_sources_ifdef(CONFIG_NXP_IRQSTEER intc_nxp_irqsteer.c)
drivers/interrupt_controller: Add fault event support on Intel VT-D IR faults are non-recoverable, so it's good to know why. Thus let's handle the fault event and print the fault. Other faults are printed as well. Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2021-01-07 14:10:48 +01:00
if(CONFIG_INTEL_VTD_ICTL)
zephyr_library_include_directories(${ZEPHYR_BASE}/arch/x86/include)
endif()
drivers: plic: support multiple instances for multi-level Most of the public APIs in `riscv_plic.h` (except `riscv_plic_get_irq` & `riscv_plic_get_dev`) expect the `irq` argument to be in Zephyr-encoded format, instead of the previously `irq_from_level_2`-stripped version. The first level IRQ is needed by `intc_plic` to differentiate between the parent interrupt controllers, so that correct ISR offset can be obtained using the LUT in `sw_isr_common`. Signed-off-by: Yong Cong Sin <ycsin@meta.com>
2023-09-20 12:01:35 +02:00
drivers: intc: plic: add shell cmd to get irq stats for debugging Introduced `CONFIG_PLIC_SHELL` to enable the build of shell debugging command to get the hit count of each interrupt controller's IRQ line. This is especially useful when working with dynamically installed ISRs, which will be the case for `plic_sw`. Example usage: ``` uart:~$ plic stats get interrupt-controller@c000000 IRQ Hits ================== 10 177 uart:~$ plic stats get interrupt-controller@c000000 IRQ Hits ================== 10 236 uart:~$ plic stats clear interrupt-controller@c000000 Cleared stats of interrupt-controller@c000000. uart:~$ plic stats get interrupt-controller@c000000 IRQ Hits ================== 10 90 ``` Signed-off-by: Yong Cong Sin <ycsin@meta.com> Signed-off-by: Maxim Adelman <imax@meta.com>
2023-11-21 15:53:01 +01:00
if(CONFIG_PLIC_SHELL)
message(WARNING "
WARNING: `CONFIG_PLIC_SHELL` is enabled.
This can use quite a bit of RAM (PLICs * IRQs * sizeof(uint16_t))"
)
endif()
drivers: plic: support multiple instances for multi-level Most of the public APIs in `riscv_plic.h` (except `riscv_plic_get_irq` & `riscv_plic_get_dev`) expect the `irq` argument to be in Zephyr-encoded format, instead of the previously `irq_from_level_2`-stripped version. The first level IRQ is needed by `intc_plic` to differentiate between the parent interrupt controllers, so that correct ISR offset can be obtained using the LUT in `sw_isr_common`. Signed-off-by: Yong Cong Sin <ycsin@meta.com>
2023-09-20 12:01:35 +02:00
zephyr_library_include_directories(${ZEPHYR_BASE}/arch/common/include)
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