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zephyr/dts/x86/elkhart_lake.dtsi

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soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-10 19:08:37 +01:00
/*
* Copyright (c) 2020 Intel Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "skeleton.dtsi"
#include <dt-bindings/interrupt-controller/intel-ioapic.h>
#include <dt-bindings/i2c/i2c.h>
#include <dt-bindings/pcie/pcie.h>
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "elkhart_lake";
reg = <0>;
};
};
dram0: memory@0 {
device_type = "memory";
reg = <0x0 DT_DRAM_SIZE>;
};
edac: Move IBECC information to DT root Move EDAC/IBECC data to Device Tree root. Signed-off-by: Andrei Emeltchenko <andrei.emeltchenko@intel.com>
2021-01-25 16:04:03 +01:00
ibecc: ibecc {
compatible = "intel,ibecc";
label = "ibecc";
status = "okay";
};
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-10 19:08:37 +01:00
intc: ioapic@fec00000 {
compatible = "intel,ioapic";
reg = <0xfec00000 0x1000>;
interrupt-controller;
#interrupt-cells = <3>;
};
drivers: uart: ns16550: Move all PCIe-using nodes to a PCIe bus in DTS The existing method of testing for any of the first four DT instances having the pcie property feels a bit clumsy and will get more so when support for more than four UARTs is added. A much more cleaner way to do this (and more correct probably as well) is to list any PCIe-based UART nodes under a pcie bus in the Device Tree hierarchy. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-19 16:37:24 +01:00
pcie0 {
label = "PCIE_0";
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-10 19:08:37 +01:00
#address-cells = <1>;
#size-cells = <1>;
drivers: uart: ns16550: Move all PCIe-using nodes to a PCIe bus in DTS The existing method of testing for any of the first four DT instances having the pcie property feels a bit clumsy and will get more so when support for more than four UARTs is added. A much more cleaner way to do this (and more correct probably as well) is to list any PCIe-based UART nodes under a pcie bus in the Device Tree hierarchy. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-19 16:37:24 +01:00
compatible = "intel,pcie";
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-10 19:08:37 +01:00
ranges;
uart0: uart@f000 {
compatible = "ns16550";
reg = <PCIE_BDF(0,0x1e,0) PCIE_ID(0x8086,0x4b28)>;
label = "UART_0";
clock-frequency = <1843200>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
status = "okay";
current-speed = <115200>;
};
uart1: uart@f100 {
compatible = "ns16550";
reg = <PCIE_BDF(0,0x1e,1) PCIE_ID(0x8086,0x4b29)>;
label = "UART_1";
clock-frequency = <1843200>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
status = "okay";
current-speed = <115200>;
};
uart2: uart@ca00 {
compatible = "ns16550";
reg = <PCIE_BDF(0,0x19,2) PCIE_ID(0x8086,0x4b4d)>;
label = "UART_2";
clock-frequency = <1843200>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
status = "okay";
current-speed = <115200>;
};
uart_pse_0: uart@8800 {
compatible = "ns16550";
reg = <PCIE_BDF(0,0x11,0) PCIE_ID(0x8086,0x4b96)>;
label = "UART_PSE_0";
clock-frequency = <1843200>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
soc: x86: elkhart_lake: Update UART definitions Add definitions for UART1/2 when they're accessible through fixed MMIO addresses (instead of PCIe), and mark all UARTs not normally available with the UEFI BIOS as "disabled". Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-21 15:24:15 +01:00
status = "disabled";
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-10 19:08:37 +01:00
current-speed = <115200>;
};
uart_pse_1: uart@8900 {
compatible = "ns16550";
reg = <PCIE_BDF(0,0x11,1) PCIE_ID(0x8086,0x4b97)>;
label = "UART_PSE_1";
clock-frequency = <1843200>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
soc: x86: elkhart_lake: Update UART definitions Add definitions for UART1/2 when they're accessible through fixed MMIO addresses (instead of PCIe), and mark all UARTs not normally available with the UEFI BIOS as "disabled". Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-21 15:24:15 +01:00
status = "disabled";
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-10 19:08:37 +01:00
current-speed = <115200>;
};
uart_pse_2: uart@8a00 {
compatible = "ns16550";
reg = <PCIE_BDF(0,0x11,2) PCIE_ID(0x8086,0x4b98)>;
label = "UART_PSE_2";
clock-frequency = <1843200>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
soc: x86: elkhart_lake: Update UART definitions Add definitions for UART1/2 when they're accessible through fixed MMIO addresses (instead of PCIe), and mark all UARTs not normally available with the UEFI BIOS as "disabled". Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-21 15:24:15 +01:00
status = "disabled";
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-10 19:08:37 +01:00
current-speed = <115200>;
};
uart_pse_3: uart@8b00 {
compatible = "ns16550";
reg = <PCIE_BDF(0,0x11,3) PCIE_ID(0x8086,0x4b99)>;
label = "UART_PSE_3";
clock-frequency = <1843200>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
soc: x86: elkhart_lake: Update UART definitions Add definitions for UART1/2 when they're accessible through fixed MMIO addresses (instead of PCIe), and mark all UARTs not normally available with the UEFI BIOS as "disabled". Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-21 15:24:15 +01:00
status = "disabled";
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-10 19:08:37 +01:00
current-speed = <115200>;
};
uart_pse_4: uart@8c00 {
compatible = "ns16550";
reg = <PCIE_BDF(0,0x11,4) PCIE_ID(0x8086,0x4b9a)>;
label = "UART_PSE_4";
clock-frequency = <1843200>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
soc: x86: elkhart_lake: Update UART definitions Add definitions for UART1/2 when they're accessible through fixed MMIO addresses (instead of PCIe), and mark all UARTs not normally available with the UEFI BIOS as "disabled". Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-21 15:24:15 +01:00
status = "disabled";
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-10 19:08:37 +01:00
current-speed = <115200>;
};
uart_pse_5: uart@8d00 {
compatible = "ns16550";
reg = <PCIE_BDF(0,0x11,5) PCIE_ID(0x8086,0x4b9b)>;
label = "UART_PSE_5";
clock-frequency = <1843200>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
soc: x86: elkhart_lake: Update UART definitions Add definitions for UART1/2 when they're accessible through fixed MMIO addresses (instead of PCIe), and mark all UARTs not normally available with the UEFI BIOS as "disabled". Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-21 15:24:15 +01:00
status = "disabled";
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-10 19:08:37 +01:00
current-speed = <115200>;
};
soc: x86: elkhart_lake: Update UART definitions Add definitions for UART1/2 when they're accessible through fixed MMIO addresses (instead of PCIe), and mark all UARTs not normally available with the UEFI BIOS as "disabled". Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-21 15:24:15 +01:00
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-10 19:08:37 +01:00
i2c0: i2c@a800 {
compatible = "snps,designware-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <PCIE_BDF(0,0x15,0) PCIE_ID(0x8086,0x4b78)>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
label = "I2C_0";
status = "okay";
};
i2c1: i2c@a900 {
compatible = "snps,designware-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <PCIE_BDF(0,0x15,1) PCIE_ID(0x8086,0x4b79)>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
label = "I2C_1";
status = "okay";
};
i2c2: i2c@aa00 {
compatible = "snps,designware-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <PCIE_BDF(0,0x15,2) PCIE_ID(0x8086,0x4b7a)>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
label = "I2C_2";
status = "okay";
};
i2c3: i2c@ab00 {
compatible = "snps,designware-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <PCIE_BDF(0,0x15,3) PCIE_ID(0x8086,0x4b7b)>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
label = "I2C_3";
status = "okay";
};
i2c4: i2c@c800 {
compatible = "snps,designware-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <PCIE_BDF(0,0x19,0) PCIE_ID(0x8086,0x4b4b)>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
label = "I2C_4";
status = "okay";
};
i2c5: i2c@c900 {
compatible = "snps,designware-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <PCIE_BDF(0,0x19,1) PCIE_ID(0x8086,0x4b4c)>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
label = "I2C_5";
status = "okay";
};
i2c6: i2c@8000 {
compatible = "snps,designware-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <PCIE_BDF(0,0x10,0) PCIE_ID(0x8086,0x4b44)>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
label = "I2C_6";
status = "okay";
};
i2c7: i2c@8100 {
compatible = "snps,designware-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <PCIE_BDF(0,0x10,1) PCIE_ID(0x8086,0x4b45)>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
label = "I2C_7";
status = "okay";
};
i2c_pse_0: i2c@d800 {
compatible = "snps,designware-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <PCIE_BDF(0,0x1b,0) PCIE_ID(0x8086,0x4bb9)>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
label = "I2C_PSE_0";
status = "okay";
};
i2c_pse_1: i2c@d900 {
compatible = "snps,designware-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <PCIE_BDF(0,0x1b,1) PCIE_ID(0x8086,0x4bba)>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
label = "I2C_PSE_1";
status = "okay";
};
i2c_pse_2: i2c@da00 {
compatible = "snps,designware-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <PCIE_BDF(0,0x1b,2) PCIE_ID(0x8086,0x4bbb)>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
label = "I2C_PSE_2";
status = "okay";
};
i2c_pse_3: i2c@db00 {
compatible = "snps,designware-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <PCIE_BDF(0,0x1b,3) PCIE_ID(0x8086,0x4bbc)>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
label = "I2C_PSE_3";
status = "okay";
};
i2c_pse_4: i2c@dc00 {
compatible = "snps,designware-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <PCIE_BDF(0,0x1b,4) PCIE_ID(0x8086,0x4bbd)>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
label = "I2C_PSE_4";
status = "okay";
};
i2c_pse_5: i2c@dd00 {
compatible = "snps,designware-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <PCIE_BDF(0,0x1b,5) PCIE_ID(0x8086,0x4bbe)>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
label = "I2C_PSE_5";
status = "okay";
};
i2c_pse_6: i2c@de00 {
compatible = "snps,designware-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <PCIE_BDF(0,0x1b,6) PCIE_ID(0x8086,0x4bbf)>;
interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
label = "I2C_PSE_6";
status = "okay";
};
drivers: i2c_dw: User proper PCIe DT hierarchy Move all PCIe-based DT nodes under a PCIe bus and take advantage of the DT_ANY_INST_ON_BUS_STATUS_OKAY() and DT_INST_ON_BUS() macros. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2021-01-19 11:46:43 +01:00
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges;
uart1_fixed: uart@fe040000 {
compatible = "ns16550";
reg = <0xfe040000 0x1000>;
reg-shift = <0>;
label = "UART_1_FIXED";
clock-frequency = <1843200>;
interrupts = <3 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
status = "disabled";
current-speed = <115200>;
};
uart2_fixed: uart@fe042000 {
compatible = "ns16550";
reg = <0xfe042000 0x1000>;
reg-shift = <0>;
label = "UART_2_FIXED";
clock-frequency = <1843200>;
interrupts = <4 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
interrupt-parent = <&intc>;
status = "disabled";
current-speed = <115200>;
};
soc: x86: Add Elkhart Lake SoC definition Add a basic definition for the Intel Elkhart Lake SoC. Signed-off-by: Johan Hedberg <johan.hedberg@intel.com>
2020-12-10 19:08:37 +01:00
hpet: hpet@fed00000 {
label = "HPET";
compatible = "intel,hpet";
reg = <0xfed00000 0x400>;
interrupts = <2 IRQ_TYPE_FIXED_EDGE_RISING 4>;
interrupt-parent = <&intc>;
status = "okay";
};
};
};
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