driver: reset: npcx: add driver support for reset controller
Nuvoton NPCX chips have reset registers which allow to reset the peripheral hardware modules. This commit adds the support by implementing the reset driver. Note that only the reset_line_toggle API is supported because of the nature of the reset controller's design. Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
This commit is contained in:
Jun Lin
Alberto Escolar
parent
e10ed057e8
commit
011b730b4c
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@ -9,3 +9,4 @@ zephyr_library_sources_ifdef(CONFIG_RESET_AST10X0 reset_ast10x0.c)
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zephyr_library_sources_ifdef(CONFIG_RESET_STM32 reset_stm32.c)
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zephyr_library_sources_ifdef(CONFIG_RESET_NUMAKER reset_numaker.c)
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zephyr_library_sources_ifdef(CONFIG_RESET_INTEL_SOCFPGA reset_intel_socfpga.c)
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zephyr_library_sources_ifdef(CONFIG_RESET_NPCX reset_npcx.c)
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@ -33,5 +33,6 @@ rsource "Kconfig.aspeed"
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rsource "Kconfig.stm32"
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rsource "Kconfig.numaker"
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rsource "Kconfig.intel_socfpga"
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rsource "Kconfig.npcx"
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endif # RESET
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11
drivers/reset/Kconfig.npcx
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11
drivers/reset/Kconfig.npcx
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@ -0,0 +1,11 @@
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# NPCX reset controller driver configuration options
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# Copyright (c) 2024 Nuvoton Technology Corporation.
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# SPDX-License-Identifier: Apache-2.0
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config RESET_NPCX
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bool "Nuvoton NPCX embedded controller (EC) reset controller driver"
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default y
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depends on DT_HAS_NUVOTON_NPCX_RST_ENABLED
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help
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This option enables the reset controller driver for Nuvoton NPCX MCUs.
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78
drivers/reset/reset_npcx.c
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78
drivers/reset/reset_npcx.c
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@ -0,0 +1,78 @@
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/*
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* Copyright (c) 2024 Nuvoton Technology Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT nuvoton_npcx_rst
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#include <zephyr/kernel.h>
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#include <zephyr/drivers/reset.h>
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#if defined(CONFIG_SOC_SERIES_NPCX7)
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#include <zephyr/dt-bindings/reset/npcx7_reset.h>
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#elif defined(CONFIG_SOC_SERIES_NPCX9)
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#include <zephyr/dt-bindings/reset/npcx9_reset.h>
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#elif defined(CONFIG_SOC_SERIES_NPCX4)
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#include <zephyr/dt-bindings/reset/npcx4_reset.h>
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#endif
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(rst_npcx);
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#define NPCX_RESET_CTL_REG_BYTE_SIZE 4
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#define NPCX_RESET_CTL_REG_OFFSET(id) ((id) >> (NPCX_RESET_CTL_REG_BYTE_SIZE + 1))
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#define NPCX_RESET_CTL_REG_BIT(id) (((id) & ((1 << (NPCX_RESET_CTL_REG_BYTE_SIZE + 1)) - 1)))
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#define NPCX_SWRST_TRG_WORD_START 0xC183
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#define NPCX_SWRST_TRG_WORD_CLEAR 0x0
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#define NPCX_SWRST_TRG_WORD_DONE 0xFFFF
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#define NPCX_SWRST_DONE_TIMEOUT_US 100
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struct reset_npcx_dev_config {
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struct swrst_reg *reg_base;
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};
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static int reset_npcx_line_toggle(const struct device *dev, uint32_t id)
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{
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const struct reset_npcx_dev_config *const config = dev->config;
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struct swrst_reg *const reg = config->reg_base;
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unsigned int key;
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uint8_t reg_offset;
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uint8_t reg_bit;
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int ret = 0;
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if (!IN_RANGE(id, NPCX_RESET_ID_START, NPCX_RESET_ID_END)) {
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LOG_ERR("Invalid Reset ID");
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return -EINVAL;
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}
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reg_offset = NPCX_RESET_CTL_REG_OFFSET(id);
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reg_bit = NPCX_RESET_CTL_REG_BIT(id);
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key = irq_lock();
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reg->SWRST_CTL[reg_offset] |= BIT(reg_bit);
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reg->SWRST_TRG = NPCX_SWRST_TRG_WORD_CLEAR;
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reg->SWRST_TRG = NPCX_SWRST_TRG_WORD_START;
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if (!WAIT_FOR((reg->SWRST_TRG == NPCX_SWRST_TRG_WORD_DONE), NPCX_SWRST_DONE_TIMEOUT_US,
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NULL)) {
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LOG_ERR("Reset trig timeout");
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ret = -EBUSY;
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}
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irq_unlock(key);
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return ret;
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}
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static const struct reset_driver_api reset_npcx_driver_api = {
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.line_toggle = reset_npcx_line_toggle,
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};
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static const struct reset_npcx_dev_config reset_npcx_config = {
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.reg_base = (struct swrst_reg *)DT_INST_REG_ADDR(0),
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};
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DEVICE_DT_INST_DEFINE(0, NULL, NULL, NULL, &reset_npcx_config, PRE_KERNEL_1,
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CONFIG_RESET_INIT_PRIORITY, &reset_npcx_driver_api);
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@ -317,6 +317,13 @@
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status = "disabled";
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};
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};
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rctl: reset-controller@400c3100 {
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compatible = "nuvoton,npcx-rst";
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reg = <0x400c3100 0x14>;
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#reset-cells = <1>;
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status = "disabled";
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};
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};
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soc-if {
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@ -260,6 +260,13 @@
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rx-plsize = <64>;
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tx-plsize = <16>;
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};
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rctl: reset-controller@400c3100 {
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compatible = "nuvoton,npcx-rst";
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reg = <0x400c3100 0x10>;
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#reset-cells = <1>;
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status = "disabled";
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};
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};
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soc-id {
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@ -288,6 +288,13 @@
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rx-plsize = <64>;
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tx-plsize = <16>;
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};
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rctl: reset-controller@400c3100 {
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compatible = "nuvoton,npcx-rst";
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reg = <0x400c3100 0x14>;
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#reset-cells = <1>;
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status = "disabled";
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};
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};
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soc-id {
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18
dts/bindings/reset/nuvoton,npcx-rst.yaml
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18
dts/bindings/reset/nuvoton,npcx-rst.yaml
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@ -0,0 +1,18 @@
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# Copyright (c) 2024 Nuvoton Technology Corporation.
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# SPDX-License-Identifier: Apache-2.0
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description: NPCX Reset Controller
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compatible: "nuvoton,npcx-rst"
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include: [reset-controller.yaml, base.yaml]
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properties:
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reg:
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required: true
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"#reset-cells":
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const: 1
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reset-cells:
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- id
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114
include/zephyr/dt-bindings/reset/npcx4_reset.h
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114
include/zephyr/dt-bindings/reset/npcx4_reset.h
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@ -0,0 +1,114 @@
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/*
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* Copyright (c) 2024 Nuvoton Technology Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_NPCX4_RESET_H
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#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_NPCX4_RESET_H
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#define NPCX_RESET_SWRST_CTL1_OFFSET 0
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#define NPCX_RESET_SWRST_CTL2_OFFSET 32
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#define NPCX_RESET_SWRST_CTL3_OFFSET 64
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#define NPCX_RESET_SWRST_CTL4_OFFSET 96
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#define NPCX_RESET_GPIO0 (NPCX_RESET_SWRST_CTL1_OFFSET + 0)
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#define NPCX_RESET_GPIO1 (NPCX_RESET_SWRST_CTL1_OFFSET + 1)
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#define NPCX_RESET_GPIO2 (NPCX_RESET_SWRST_CTL1_OFFSET + 2)
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#define NPCX_RESET_GPIO3 (NPCX_RESET_SWRST_CTL1_OFFSET + 3)
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#define NPCX_RESET_GPIO4 (NPCX_RESET_SWRST_CTL1_OFFSET + 4)
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#define NPCX_RESET_GPIO5 (NPCX_RESET_SWRST_CTL1_OFFSET + 5)
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#define NPCX_RESET_GPIO6 (NPCX_RESET_SWRST_CTL1_OFFSET + 6)
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#define NPCX_RESET_GPIO7 (NPCX_RESET_SWRST_CTL1_OFFSET + 7)
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#define NPCX_RESET_GPIO8 (NPCX_RESET_SWRST_CTL1_OFFSET + 8)
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#define NPCX_RESET_GPIO9 (NPCX_RESET_SWRST_CTL1_OFFSET + 9)
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#define NPCX_RESET_GPIOA (NPCX_RESET_SWRST_CTL1_OFFSET + 10)
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#define NPCX_RESET_GPIOB (NPCX_RESET_SWRST_CTL1_OFFSET + 11)
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#define NPCX_RESET_GPIOC (NPCX_RESET_SWRST_CTL1_OFFSET + 12)
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#define NPCX_RESET_GPIOD (NPCX_RESET_SWRST_CTL1_OFFSET + 13)
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#define NPCX_RESET_GPIOE (NPCX_RESET_SWRST_CTL1_OFFSET + 14)
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#define NPCX_RESET_GPIOF (NPCX_RESET_SWRST_CTL1_OFFSET + 15)
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#define NPCX_RESET_ITIM64 (NPCX_RESET_SWRST_CTL1_OFFSET + 16)
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#define NPCX_RESET_ITIM32_1 (NPCX_RESET_SWRST_CTL1_OFFSET + 18)
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#define NPCX_RESET_ITIM32_2 (NPCX_RESET_SWRST_CTL1_OFFSET + 19)
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#define NPCX_RESET_ITIM32_3 (NPCX_RESET_SWRST_CTL1_OFFSET + 20)
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#define NPCX_RESET_ITIM32_4 (NPCX_RESET_SWRST_CTL1_OFFSET + 21)
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#define NPCX_RESET_ITIM32_5 (NPCX_RESET_SWRST_CTL1_OFFSET + 22)
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#define NPCX_RESET_ITIM32_6 (NPCX_RESET_SWRST_CTL1_OFFSET + 23)
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#define NPCX_RESET_MTC (NPCX_RESET_SWRST_CTL1_OFFSET + 25)
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#define NPCX_RESET_MIWU0 (NPCX_RESET_SWRST_CTL1_OFFSET + 26)
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#define NPCX_RESET_MIWU1 (NPCX_RESET_SWRST_CTL1_OFFSET + 27)
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#define NPCX_RESET_MIWU2 (NPCX_RESET_SWRST_CTL1_OFFSET + 28)
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#define NPCX_RESET_GDMA1 (NPCX_RESET_SWRST_CTL1_OFFSET + 29)
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#define NPCX_RESET_GDMA2 (NPCX_RESET_SWRST_CTL1_OFFSET + 30)
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#define NPCX_RESET_PMC (NPCX_RESET_SWRST_CTL2_OFFSET + 0)
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#define NPCX_RESET_SHI (NPCX_RESET_SWRST_CTL2_OFFSET + 2)
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#define NPCX_RESET_SPIP (NPCX_RESET_SWRST_CTL2_OFFSET + 3)
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#define NPCX_RESET_ADCE (NPCX_RESET_SWRST_CTL2_OFFSET + 4)
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#define NPCX_RESET_PECI (NPCX_RESET_SWRST_CTL2_OFFSET + 5)
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#define NPCX_RESET_CRUART2 (NPCX_RESET_SWRST_CTL2_OFFSET + 6)
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#define NPCX_RESET_ADCI (NPCX_RESET_SWRST_CTL2_OFFSET + 7)
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#define NPCX_RESET_SMB0 (NPCX_RESET_SWRST_CTL2_OFFSET + 8)
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#define NPCX_RESET_SMB1 (NPCX_RESET_SWRST_CTL2_OFFSET + 9)
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#define NPCX_RESET_SMB2 (NPCX_RESET_SWRST_CTL2_OFFSET + 10)
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#define NPCX_RESET_SMB3 (NPCX_RESET_SWRST_CTL2_OFFSET + 11)
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#define NPCX_RESET_SMB4 (NPCX_RESET_SWRST_CTL2_OFFSET + 12)
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#define NPCX_RESET_SMB5 (NPCX_RESET_SWRST_CTL2_OFFSET + 13)
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#define NPCX_RESET_SMB6 (NPCX_RESET_SWRST_CTL2_OFFSET + 14)
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#define NPCX_RESET_TWD (NPCX_RESET_SWRST_CTL2_OFFSET + 15)
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#define NPCX_RESET_PWM0 (NPCX_RESET_SWRST_CTL2_OFFSET + 16)
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#define NPCX_RESET_PWM1 (NPCX_RESET_SWRST_CTL2_OFFSET + 17)
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#define NPCX_RESET_PWM2 (NPCX_RESET_SWRST_CTL2_OFFSET + 18)
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#define NPCX_RESET_PWM3 (NPCX_RESET_SWRST_CTL2_OFFSET + 19)
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#define NPCX_RESET_PWM4 (NPCX_RESET_SWRST_CTL2_OFFSET + 20)
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#define NPCX_RESET_PWM5 (NPCX_RESET_SWRST_CTL2_OFFSET + 21)
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#define NPCX_RESET_PWM6 (NPCX_RESET_SWRST_CTL2_OFFSET + 22)
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#define NPCX_RESET_PWM7 (NPCX_RESET_SWRST_CTL2_OFFSET + 23)
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#define NPCX_RESET_MFT16_1 (NPCX_RESET_SWRST_CTL2_OFFSET + 24)
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#define NPCX_RESET_MFT16_2 (NPCX_RESET_SWRST_CTL2_OFFSET + 25)
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#define NPCX_RESET_MFT16_3 (NPCX_RESET_SWRST_CTL2_OFFSET + 26)
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#define NPCX_RESET_SMB7 (NPCX_RESET_SWRST_CTL2_OFFSET + 27)
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#define NPCX_RESET_CRUART1 (NPCX_RESET_SWRST_CTL2_OFFSET + 28)
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#define NPCX_RESET_PS2 (NPCX_RESET_SWRST_CTL2_OFFSET + 29)
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#define NPCX_RESET_SDP (NPCX_RESET_SWRST_CTL2_OFFSET + 30)
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#define NPCX_RESET_KBS (NPCX_RESET_SWRST_CTL2_OFFSET + 31)
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#define NPCX_RESET_SIOCFG (NPCX_RESET_SWRST_CTL3_OFFSET + 0)
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#define NPCX_RESET_SERPORT (NPCX_RESET_SWRST_CTL3_OFFSET + 1)
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#define NPCX_RESET_I3C_1 (NPCX_RESET_SWRST_CTL3_OFFSET + 4)
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#define NPCX_RESET_I3C_2 (NPCX_RESET_SWRST_CTL3_OFFSET + 5)
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#define NPCX_RESET_I3C_3 (NPCX_RESET_SWRST_CTL3_OFFSET + 6)
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#define NPCX_RESET_I3C_RD (NPCX_RESET_SWRST_CTL3_OFFSET + 7)
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#define NPCX_RESET_MSWC (NPCX_RESET_SWRST_CTL3_OFFSET + 8)
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#define NPCX_RESET_SHM (NPCX_RESET_SWRST_CTL3_OFFSET + 9)
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#define NPCX_RESET_PMCH1 (NPCX_RESET_SWRST_CTL3_OFFSET + 10)
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#define NPCX_RESET_PMCH2 (NPCX_RESET_SWRST_CTL3_OFFSET + 11)
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#define NPCX_RESET_PMCH3 (NPCX_RESET_SWRST_CTL3_OFFSET + 12)
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#define NPCX_RESET_PMCH4 (NPCX_RESET_SWRST_CTL3_OFFSET + 13)
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#define NPCX_RESET_KBC (NPCX_RESET_SWRST_CTL3_OFFSET + 15)
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#define NPCX_RESET_C2HOST (NPCX_RESET_SWRST_CTL3_OFFSET + 16)
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#define NPCX_RESET_CRUART3 (NPCX_RESET_SWRST_CTL3_OFFSET + 18)
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#define NPCX_RESET_CRUART4 (NPCX_RESET_SWRST_CTL3_OFFSET + 19)
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#define NPCX_RESET_LFCG (NPCX_RESET_SWRST_CTL3_OFFSET + 20)
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#define NPCX_RESET_DEV (NPCX_RESET_SWRST_CTL3_OFFSET + 22)
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#define NPCX_RESET_SYSCFG (NPCX_RESET_SWRST_CTL3_OFFSET + 23)
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#define NPCX_RESET_SBY (NPCX_RESET_SWRST_CTL3_OFFSET + 24)
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#define NPCX_RESET_BBRAM (NPCX_RESET_SWRST_CTL3_OFFSET + 25)
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#define NPCX_RESET_SHA_2B (NPCX_RESET_SWRST_CTL3_OFFSET + 26)
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#define NPCX_RESET_SHA_2A (NPCX_RESET_SWRST_CTL3_OFFSET + 29)
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#define NPCX_RESET_MDC (NPCX_RESET_SWRST_CTL4_OFFSET + 15)
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#define NPCX_RESET_FIU0 (NPCX_RESET_SWRST_CTL4_OFFSET + 16)
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#define NPCX_RESET_FIU1 (NPCX_RESET_SWRST_CTL4_OFFSET + 17)
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#define NPCX_RESET_MDMA1 (NPCX_RESET_SWRST_CTL4_OFFSET + 24)
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#define NPCX_RESET_MDMA2 (NPCX_RESET_SWRST_CTL4_OFFSET + 25)
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#define NPCX_RESET_MDMA3 (NPCX_RESET_SWRST_CTL4_OFFSET + 26)
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#define NPCX_RESET_MDMA4 (NPCX_RESET_SWRST_CTL4_OFFSET + 27)
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#define NPCX_RESET_MDMA5 (NPCX_RESET_SWRST_CTL4_OFFSET + 28)
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#define NPCX_RESET_MDMA6 (NPCX_RESET_SWRST_CTL4_OFFSET + 29)
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#define NPCX_RESET_MDMA7 (NPCX_RESET_SWRST_CTL4_OFFSET + 30)
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#define NPCX_RESET_ID_START NPCX_RESET_GPIO0
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#define NPCX_RESET_ID_END NPCX_RESET_MDMA7
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#endif
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94
include/zephyr/dt-bindings/reset/npcx7_reset.h
Normal file
94
include/zephyr/dt-bindings/reset/npcx7_reset.h
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@ -0,0 +1,94 @@
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/*
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* Copyright (c) 2024 Nuvoton Technology Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_NPCX7_RESET_H
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#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_NPCX7_RESET_H
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#define NPCX_RESET_SWRST_CTL1_OFFSET 0
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#define NPCX_RESET_SWRST_CTL2_OFFSET 32
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#define NPCX_RESET_SWRST_CTL3_OFFSET 64
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#define NPCX_RESET_GPIO0 (NPCX_RESET_SWRST_CTL1_OFFSET + 0)
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#define NPCX_RESET_GPIO1 (NPCX_RESET_SWRST_CTL1_OFFSET + 1)
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#define NPCX_RESET_GPIO2 (NPCX_RESET_SWRST_CTL1_OFFSET + 2)
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#define NPCX_RESET_GPIO3 (NPCX_RESET_SWRST_CTL1_OFFSET + 3)
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#define NPCX_RESET_GPIO4 (NPCX_RESET_SWRST_CTL1_OFFSET + 4)
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#define NPCX_RESET_GPIO5 (NPCX_RESET_SWRST_CTL1_OFFSET + 5)
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#define NPCX_RESET_GPIO6 (NPCX_RESET_SWRST_CTL1_OFFSET + 6)
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#define NPCX_RESET_GPIO7 (NPCX_RESET_SWRST_CTL1_OFFSET + 7)
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#define NPCX_RESET_GPIO8 (NPCX_RESET_SWRST_CTL1_OFFSET + 8)
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#define NPCX_RESET_GPIO9 (NPCX_RESET_SWRST_CTL1_OFFSET + 9)
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#define NPCX_RESET_GPIOA (NPCX_RESET_SWRST_CTL1_OFFSET + 10)
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#define NPCX_RESET_GPIOB (NPCX_RESET_SWRST_CTL1_OFFSET + 11)
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#define NPCX_RESET_GPIOC (NPCX_RESET_SWRST_CTL1_OFFSET + 12)
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#define NPCX_RESET_GPIOD (NPCX_RESET_SWRST_CTL1_OFFSET + 13)
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#define NPCX_RESET_GPIOE (NPCX_RESET_SWRST_CTL1_OFFSET + 14)
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#define NPCX_RESET_GPIOF (NPCX_RESET_SWRST_CTL1_OFFSET + 15)
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#define NPCX_RESET_ITIM64 (NPCX_RESET_SWRST_CTL1_OFFSET + 16)
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#define NPCX_RESET_ITIM16_1 (NPCX_RESET_SWRST_CTL1_OFFSET + 18)
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#define NPCX_RESET_ITIM16_2 (NPCX_RESET_SWRST_CTL1_OFFSET + 19)
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#define NPCX_RESET_ITIM16_3 (NPCX_RESET_SWRST_CTL1_OFFSET + 20)
|
||||
#define NPCX_RESET_ITIM16_4 (NPCX_RESET_SWRST_CTL1_OFFSET + 21)
|
||||
#define NPCX_RESET_ITIM16_5 (NPCX_RESET_SWRST_CTL1_OFFSET + 22)
|
||||
#define NPCX_RESET_ITIM16_6 (NPCX_RESET_SWRST_CTL1_OFFSET + 23)
|
||||
#define NPCX_RESET_ITIM32 (NPCX_RESET_SWRST_CTL1_OFFSET + 24)
|
||||
#define NPCX_RESET_MTC (NPCX_RESET_SWRST_CTL1_OFFSET + 25)
|
||||
#define NPCX_RESET_MIWU0 (NPCX_RESET_SWRST_CTL1_OFFSET + 26)
|
||||
#define NPCX_RESET_MIWU1 (NPCX_RESET_SWRST_CTL1_OFFSET + 27)
|
||||
#define NPCX_RESET_MIWU2 (NPCX_RESET_SWRST_CTL1_OFFSET + 28)
|
||||
#define NPCX_RESET_GDMA (NPCX_RESET_SWRST_CTL1_OFFSET + 29)
|
||||
#define NPCX_RESET_FIU (NPCX_RESET_SWRST_CTL1_OFFSET + 30)
|
||||
|
||||
#define NPCX_RESET_PMC (NPCX_RESET_SWRST_CTL2_OFFSET + 0)
|
||||
#define NPCX_RESET_SHI (NPCX_RESET_SWRST_CTL2_OFFSET + 2)
|
||||
#define NPCX_RESET_SPIP (NPCX_RESET_SWRST_CTL2_OFFSET + 3)
|
||||
#define NPCX_RESET_PECI (NPCX_RESET_SWRST_CTL2_OFFSET + 5)
|
||||
#define NPCX_RESET_CRUART2 (NPCX_RESET_SWRST_CTL2_OFFSET + 6)
|
||||
#define NPCX_RESET_ADC (NPCX_RESET_SWRST_CTL2_OFFSET + 7)
|
||||
#define NPCX_RESET_SMB0 (NPCX_RESET_SWRST_CTL2_OFFSET + 8)
|
||||
#define NPCX_RESET_SMB1 (NPCX_RESET_SWRST_CTL2_OFFSET + 9)
|
||||
#define NPCX_RESET_SMB2 (NPCX_RESET_SWRST_CTL2_OFFSET + 10)
|
||||
#define NPCX_RESET_SMB3 (NPCX_RESET_SWRST_CTL2_OFFSET + 11)
|
||||
#define NPCX_RESET_SMB4 (NPCX_RESET_SWRST_CTL2_OFFSET + 12)
|
||||
#define NPCX_RESET_SMB5 (NPCX_RESET_SWRST_CTL2_OFFSET + 13)
|
||||
#define NPCX_RESET_SMB6 (NPCX_RESET_SWRST_CTL2_OFFSET + 14)
|
||||
#define NPCX_RESET_TWD (NPCX_RESET_SWRST_CTL2_OFFSET + 15)
|
||||
#define NPCX_RESET_PWM0 (NPCX_RESET_SWRST_CTL2_OFFSET + 16)
|
||||
#define NPCX_RESET_PWM1 (NPCX_RESET_SWRST_CTL2_OFFSET + 17)
|
||||
#define NPCX_RESET_PWM2 (NPCX_RESET_SWRST_CTL2_OFFSET + 18)
|
||||
#define NPCX_RESET_PWM3 (NPCX_RESET_SWRST_CTL2_OFFSET + 19)
|
||||
#define NPCX_RESET_PWM4 (NPCX_RESET_SWRST_CTL2_OFFSET + 20)
|
||||
#define NPCX_RESET_PWM5 (NPCX_RESET_SWRST_CTL2_OFFSET + 21)
|
||||
#define NPCX_RESET_PWM6 (NPCX_RESET_SWRST_CTL2_OFFSET + 22)
|
||||
#define NPCX_RESET_PWM7 (NPCX_RESET_SWRST_CTL2_OFFSET + 23)
|
||||
#define NPCX_RESET_MFT16_1 (NPCX_RESET_SWRST_CTL2_OFFSET + 24)
|
||||
#define NPCX_RESET_MFT16_2 (NPCX_RESET_SWRST_CTL2_OFFSET + 25)
|
||||
#define NPCX_RESET_MFT16_3 (NPCX_RESET_SWRST_CTL2_OFFSET + 26)
|
||||
#define NPCX_RESET_SMB7 (NPCX_RESET_SWRST_CTL2_OFFSET + 27)
|
||||
#define NPCX_RESET_CRUART1 (NPCX_RESET_SWRST_CTL2_OFFSET + 28)
|
||||
#define NPCX_RESET_PS2 (NPCX_RESET_SWRST_CTL2_OFFSET + 29)
|
||||
#define NPCX_RESET_SDP (NPCX_RESET_SWRST_CTL2_OFFSET + 30)
|
||||
#define NPCX_RESET_KBS (NPCX_RESET_SWRST_CTL2_OFFSET + 31)
|
||||
|
||||
#define NPCX_RESET_SIOCFG (NPCX_RESET_SWRST_CTL3_OFFSET + 0)
|
||||
#define NPCX_RESET_SERPORT (NPCX_RESET_SWRST_CTL3_OFFSET + 1)
|
||||
#define NPCX_RESET_MSWC (NPCX_RESET_SWRST_CTL3_OFFSET + 8)
|
||||
#define NPCX_RESET_SHM (NPCX_RESET_SWRST_CTL3_OFFSET + 9)
|
||||
#define NPCX_RESET_PMCH1 (NPCX_RESET_SWRST_CTL3_OFFSET + 10)
|
||||
#define NPCX_RESET_PMCH2 (NPCX_RESET_SWRST_CTL3_OFFSET + 11)
|
||||
#define NPCX_RESET_PMCH3 (NPCX_RESET_SWRST_CTL3_OFFSET + 12)
|
||||
#define NPCX_RESET_PMCH4 (NPCX_RESET_SWRST_CTL3_OFFSET + 13)
|
||||
#define NPCX_RESET_KBC (NPCX_RESET_SWRST_CTL3_OFFSET + 15)
|
||||
#define NPCX_RESET_C2HOST (NPCX_RESET_SWRST_CTL3_OFFSET + 16)
|
||||
#define NPCX_RESET_LFCG (NPCX_RESET_SWRST_CTL3_OFFSET + 20)
|
||||
#define NPCX_RESET_DEV (NPCX_RESET_SWRST_CTL3_OFFSET + 22)
|
||||
#define NPCX_RESET_SYSCFG (NPCX_RESET_SWRST_CTL3_OFFSET + 23)
|
||||
#define NPCX_RESET_SBY (NPCX_RESET_SWRST_CTL3_OFFSET + 24)
|
||||
#define NPCX_RESET_BBRAM (NPCX_RESET_SWRST_CTL3_OFFSET + 25)
|
||||
|
||||
#define NPCX_RESET_ID_START NPCX_RESET_GPIO0
|
||||
#define NPCX_RESET_ID_END NPCX_RESET_BBRAM
|
||||
#endif
|
||||
104
include/zephyr/dt-bindings/reset/npcx9_reset.h
Normal file
104
include/zephyr/dt-bindings/reset/npcx9_reset.h
Normal file
|
|
@ -0,0 +1,104 @@
|
|||
/*
|
||||
* Copyright (c) 2024 Nuvoton Technology Corporation.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_NPCX9_RESET_H
|
||||
#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_NPCX9_RESET_H
|
||||
|
||||
#define NPCX_RESET_SWRST_CTL1_OFFSET 0
|
||||
#define NPCX_RESET_SWRST_CTL2_OFFSET 32
|
||||
#define NPCX_RESET_SWRST_CTL3_OFFSET 64
|
||||
#define NPCX_RESET_SWRST_CTL4_OFFSET 96
|
||||
|
||||
#define NPCX_RESET_GPIO0 (NPCX_RESET_SWRST_CTL1_OFFSET + 0)
|
||||
#define NPCX_RESET_GPIO1 (NPCX_RESET_SWRST_CTL1_OFFSET + 1)
|
||||
#define NPCX_RESET_GPIO2 (NPCX_RESET_SWRST_CTL1_OFFSET + 2)
|
||||
#define NPCX_RESET_GPIO3 (NPCX_RESET_SWRST_CTL1_OFFSET + 3)
|
||||
#define NPCX_RESET_GPIO4 (NPCX_RESET_SWRST_CTL1_OFFSET + 4)
|
||||
#define NPCX_RESET_GPIO5 (NPCX_RESET_SWRST_CTL1_OFFSET + 5)
|
||||
#define NPCX_RESET_GPIO6 (NPCX_RESET_SWRST_CTL1_OFFSET + 6)
|
||||
#define NPCX_RESET_GPIO7 (NPCX_RESET_SWRST_CTL1_OFFSET + 7)
|
||||
#define NPCX_RESET_GPIO8 (NPCX_RESET_SWRST_CTL1_OFFSET + 8)
|
||||
#define NPCX_RESET_GPIO9 (NPCX_RESET_SWRST_CTL1_OFFSET + 9)
|
||||
#define NPCX_RESET_GPIOA (NPCX_RESET_SWRST_CTL1_OFFSET + 10)
|
||||
#define NPCX_RESET_GPIOB (NPCX_RESET_SWRST_CTL1_OFFSET + 11)
|
||||
#define NPCX_RESET_GPIOC (NPCX_RESET_SWRST_CTL1_OFFSET + 12)
|
||||
#define NPCX_RESET_GPIOD (NPCX_RESET_SWRST_CTL1_OFFSET + 13)
|
||||
#define NPCX_RESET_GPIOE (NPCX_RESET_SWRST_CTL1_OFFSET + 14)
|
||||
#define NPCX_RESET_GPIOF (NPCX_RESET_SWRST_CTL1_OFFSET + 15)
|
||||
#define NPCX_RESET_ITIM64 (NPCX_RESET_SWRST_CTL1_OFFSET + 16)
|
||||
#define NPCX_RESET_ITIM32_1 (NPCX_RESET_SWRST_CTL1_OFFSET + 18)
|
||||
#define NPCX_RESET_ITIM32_2 (NPCX_RESET_SWRST_CTL1_OFFSET + 19)
|
||||
#define NPCX_RESET_ITIM32_3 (NPCX_RESET_SWRST_CTL1_OFFSET + 20)
|
||||
#define NPCX_RESET_ITIM32_4 (NPCX_RESET_SWRST_CTL1_OFFSET + 21)
|
||||
#define NPCX_RESET_ITIM32_5 (NPCX_RESET_SWRST_CTL1_OFFSET + 22)
|
||||
#define NPCX_RESET_ITIM32_6 (NPCX_RESET_SWRST_CTL1_OFFSET + 23)
|
||||
#define NPCX_RESET_MTC (NPCX_RESET_SWRST_CTL1_OFFSET + 25)
|
||||
#define NPCX_RESET_MIWU0 (NPCX_RESET_SWRST_CTL1_OFFSET + 26)
|
||||
#define NPCX_RESET_MIWU1 (NPCX_RESET_SWRST_CTL1_OFFSET + 27)
|
||||
#define NPCX_RESET_MIWU2 (NPCX_RESET_SWRST_CTL1_OFFSET + 28)
|
||||
#define NPCX_RESET_GDMA (NPCX_RESET_SWRST_CTL1_OFFSET + 29)
|
||||
#define NPCX_RESET_FIU (NPCX_RESET_SWRST_CTL1_OFFSET + 30)
|
||||
|
||||
#define NPCX_RESET_PMC (NPCX_RESET_SWRST_CTL2_OFFSET + 0)
|
||||
#define NPCX_RESET_SHI (NPCX_RESET_SWRST_CTL2_OFFSET + 2)
|
||||
#define NPCX_RESET_SPIP (NPCX_RESET_SWRST_CTL2_OFFSET + 3)
|
||||
#define NPCX_RESET_PECI (NPCX_RESET_SWRST_CTL2_OFFSET + 5)
|
||||
#define NPCX_RESET_CRUART2 (NPCX_RESET_SWRST_CTL2_OFFSET + 6)
|
||||
#define NPCX_RESET_ADC (NPCX_RESET_SWRST_CTL2_OFFSET + 7)
|
||||
#define NPCX_RESET_SMB0 (NPCX_RESET_SWRST_CTL2_OFFSET + 8)
|
||||
#define NPCX_RESET_SMB1 (NPCX_RESET_SWRST_CTL2_OFFSET + 9)
|
||||
#define NPCX_RESET_SMB2 (NPCX_RESET_SWRST_CTL2_OFFSET + 10)
|
||||
#define NPCX_RESET_SMB3 (NPCX_RESET_SWRST_CTL2_OFFSET + 11)
|
||||
#define NPCX_RESET_SMB4 (NPCX_RESET_SWRST_CTL2_OFFSET + 12)
|
||||
#define NPCX_RESET_SMB5 (NPCX_RESET_SWRST_CTL2_OFFSET + 13)
|
||||
#define NPCX_RESET_SMB6 (NPCX_RESET_SWRST_CTL2_OFFSET + 14)
|
||||
#define NPCX_RESET_TWD (NPCX_RESET_SWRST_CTL2_OFFSET + 15)
|
||||
#define NPCX_RESET_PWM0 (NPCX_RESET_SWRST_CTL2_OFFSET + 16)
|
||||
#define NPCX_RESET_PWM1 (NPCX_RESET_SWRST_CTL2_OFFSET + 17)
|
||||
#define NPCX_RESET_PWM2 (NPCX_RESET_SWRST_CTL2_OFFSET + 18)
|
||||
#define NPCX_RESET_PWM3 (NPCX_RESET_SWRST_CTL2_OFFSET + 19)
|
||||
#define NPCX_RESET_PWM4 (NPCX_RESET_SWRST_CTL2_OFFSET + 20)
|
||||
#define NPCX_RESET_PWM5 (NPCX_RESET_SWRST_CTL2_OFFSET + 21)
|
||||
#define NPCX_RESET_PWM6 (NPCX_RESET_SWRST_CTL2_OFFSET + 22)
|
||||
#define NPCX_RESET_PWM7 (NPCX_RESET_SWRST_CTL2_OFFSET + 23)
|
||||
#define NPCX_RESET_MFT16_1 (NPCX_RESET_SWRST_CTL2_OFFSET + 24)
|
||||
#define NPCX_RESET_MFT16_2 (NPCX_RESET_SWRST_CTL2_OFFSET + 25)
|
||||
#define NPCX_RESET_MFT16_3 (NPCX_RESET_SWRST_CTL2_OFFSET + 26)
|
||||
#define NPCX_RESET_SMB7 (NPCX_RESET_SWRST_CTL2_OFFSET + 27)
|
||||
#define NPCX_RESET_CRUART1 (NPCX_RESET_SWRST_CTL2_OFFSET + 28)
|
||||
#define NPCX_RESET_PS2 (NPCX_RESET_SWRST_CTL2_OFFSET + 29)
|
||||
#define NPCX_RESET_SDP (NPCX_RESET_SWRST_CTL2_OFFSET + 30)
|
||||
#define NPCX_RESET_KBS (NPCX_RESET_SWRST_CTL2_OFFSET + 31)
|
||||
|
||||
#define NPCX_RESET_SIOCFG (NPCX_RESET_SWRST_CTL3_OFFSET + 0)
|
||||
#define NPCX_RESET_SERPORT (NPCX_RESET_SWRST_CTL3_OFFSET + 1)
|
||||
#define NPCX_RESET_I3C (NPCX_RESET_SWRST_CTL3_OFFSET + 5)
|
||||
#define NPCX_RESET_MSWC (NPCX_RESET_SWRST_CTL3_OFFSET + 8)
|
||||
#define NPCX_RESET_SHM (NPCX_RESET_SWRST_CTL3_OFFSET + 9)
|
||||
#define NPCX_RESET_PMCH1 (NPCX_RESET_SWRST_CTL3_OFFSET + 10)
|
||||
#define NPCX_RESET_PMCH2 (NPCX_RESET_SWRST_CTL3_OFFSET + 11)
|
||||
#define NPCX_RESET_PMCH3 (NPCX_RESET_SWRST_CTL3_OFFSET + 12)
|
||||
#define NPCX_RESET_PMCH4 (NPCX_RESET_SWRST_CTL3_OFFSET + 13)
|
||||
#define NPCX_RESET_KBC (NPCX_RESET_SWRST_CTL3_OFFSET + 15)
|
||||
#define NPCX_RESET_C2HOST (NPCX_RESET_SWRST_CTL3_OFFSET + 16)
|
||||
#define NPCX_RESET_CRUART3 (NPCX_RESET_SWRST_CTL3_OFFSET + 18)
|
||||
#define NPCX_RESET_CRUART4 (NPCX_RESET_SWRST_CTL3_OFFSET + 19)
|
||||
#define NPCX_RESET_LFCG (NPCX_RESET_SWRST_CTL3_OFFSET + 20)
|
||||
#define NPCX_RESET_DEV (NPCX_RESET_SWRST_CTL3_OFFSET + 22)
|
||||
#define NPCX_RESET_SYSCFG (NPCX_RESET_SWRST_CTL3_OFFSET + 23)
|
||||
#define NPCX_RESET_SBY (NPCX_RESET_SWRST_CTL3_OFFSET + 24)
|
||||
#define NPCX_RESET_BBRAM (NPCX_RESET_SWRST_CTL3_OFFSET + 25)
|
||||
#define NPCX_RESET_SHA (NPCX_RESET_SWRST_CTL3_OFFSET + 29)
|
||||
|
||||
#define NPCX_RESET_MDMA1 (NPCX_RESET_SWRST_CTL4_OFFSET + 24)
|
||||
#define NPCX_RESET_MDMA2 (NPCX_RESET_SWRST_CTL4_OFFSET + 25)
|
||||
#define NPCX_RESET_MDMA3 (NPCX_RESET_SWRST_CTL4_OFFSET + 26)
|
||||
#define NPCX_RESET_MDMA4 (NPCX_RESET_SWRST_CTL4_OFFSET + 27)
|
||||
#define NPCX_RESET_MDMA5 (NPCX_RESET_SWRST_CTL4_OFFSET + 28)
|
||||
|
||||
#define NPCX_RESET_ID_START NPCX_RESET_GPIO0
|
||||
#define NPCX_RESET_ID_END NPCX_RESET_MDMA5
|
||||
#endif
|
||||
|
|
@ -1756,4 +1756,12 @@ struct spip_reg {
|
|||
#define NPCX_SPIP_STAT_BSY 0
|
||||
#define NPCX_SPIP_STAT_RBF 1
|
||||
|
||||
/* Software-triggered Pheripheral Reset Controller Register */
|
||||
struct swrst_reg {
|
||||
/* 0x000: Software Reset Trigger */
|
||||
volatile uint16_t SWRST_TRG;
|
||||
volatile uint8_t reserved1[2];
|
||||
volatile uint32_t SWRST_CTL[4];
|
||||
};
|
||||
|
||||
#endif /* _NUVOTON_NPCX_REG_DEF_H */
|
||||
|
|
|
|||
|
|
@ -189,3 +189,11 @@ NPCX_REG_OFFSET_CHECK(kbs_reg, KBS_BUF_INDX, 0x00a);
|
|||
/* SPIP register structure check */
|
||||
NPCX_REG_SIZE_CHECK(spip_reg, 0x006);
|
||||
NPCX_REG_OFFSET_CHECK(spip_reg, SPIP_CTL1, 0x002);
|
||||
|
||||
/* SWRST register structure check */
|
||||
NPCX_REG_SIZE_CHECK(swrst_reg, 0x014);
|
||||
NPCX_REG_OFFSET_CHECK(swrst_reg, SWRST_TRG, 0x000);
|
||||
NPCX_REG_OFFSET_CHECK(swrst_reg, SWRST_CTL[0], 0x004);
|
||||
NPCX_REG_OFFSET_CHECK(swrst_reg, SWRST_CTL[1], 0x008);
|
||||
NPCX_REG_OFFSET_CHECK(swrst_reg, SWRST_CTL[2], 0x00c);
|
||||
NPCX_REG_OFFSET_CHECK(swrst_reg, SWRST_CTL[3], 0x010);
|
||||
|
|
|
|||
Loading…
Reference in a new issue