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drivers/clock_control: stm32 common fix STM32_SRC_PLLCLK calculation

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Some Series were calculating the pll output frequency from an
clock source index instead of the clock source frequency.

This commit resolves this issue for l0, l1.

get_pllout_frequency() is only used for PLLCLK, therefore remove it.
F2, F4, and F7 have several pll dividers and might decide to implement
these as clock sources won't need PLLCLK.

Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
This commit is contained in:
Thomas Stranger 2022-06-29 16:12:43 +02:00 committed by Carles Cufí
parent 0d3c70ea97
commit 0d7abdf012
2 changed files with 17 additions and 13 deletions
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12
drivers/clock_control/clock_stm32f2_f4_f7.c
View file

@ -61,18 +61,6 @@ void config_pll_sysclock(void)
pllp(STM32_PLL_P_DIVISOR));
}
/**
* @brief Return pllout frequency
*/
__unused
uint32_t get_pllout_frequency(void)
{
return __LL_RCC_CALC_PLLCLK_FREQ(get_pll_source(),
pllm(STM32_PLL_M_DIVISOR),
STM32_PLL_N_MULTIPLIER,
pllp(STM32_PLL_P_DIVISOR));
}
#endif /* defined(STM32_PLL_ENABLED) */
/**

18
drivers/clock_control/clock_stm32l0_l1.c
View file

@ -41,6 +41,22 @@ static uint32_t get_pll_source(void)
return 0;
}
/**
* @brief get the pll source frequency
*/
__unused
uint32_t get_pllsrc_frequency(void)
{
if (IS_ENABLED(STM32_PLL_SRC_HSI)) {
return STM32_HSI_FREQ;
} else if (IS_ENABLED(STM32_PLL_SRC_HSE)) {
return STM32_HSE_FREQ;
}
__ASSERT(0, "Invalid source");
return 0;
}
/**
* @brief Set up pll configuration
*/
@ -58,7 +74,7 @@ void config_pll_sysclock(void)
__unused
uint32_t get_pllout_frequency(void)
{
return __LL_RCC_CALC_PLLCLK_FREQ(get_pll_source(),
return __LL_RCC_CALC_PLLCLK_FREQ(get_pllsrc_frequency(),
pll_mul(STM32_PLL_MULTIPLIER),
pll_div(STM32_PLL_DIVISOR));
}