0d7abdf012
Some Series were calculating the pll output frequency from an clock source index instead of the clock source frequency. This commit resolves this issue for l0, l1. get_pllout_frequency() is only used for PLLCLK, therefore remove it. F2, F4, and F7 have several pll dividers and might decide to implement these as clock sources won't need PLLCLK. Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
74 lines
1.4 KiB
C
74 lines
1.4 KiB
C
/*
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*
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* Copyright (c) 2017 Linaro Limited.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <soc.h>
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#include <stm32_ll_bus.h>
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#include <stm32_ll_rcc.h>
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#include <stm32_ll_utils.h>
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/sys/util.h>
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#include <zephyr/drivers/clock_control/stm32_clock_control.h>
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#include "clock_stm32_ll_common.h"
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#if defined(STM32_PLL_ENABLED)
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/**
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* @brief Return PLL source
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*/
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__unused
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static uint32_t get_pll_source(void)
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{
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if (IS_ENABLED(STM32_PLL_SRC_HSI)) {
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return LL_RCC_PLLSOURCE_HSI;
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} else if (IS_ENABLED(STM32_PLL_SRC_HSE)) {
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return LL_RCC_PLLSOURCE_HSE;
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}
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__ASSERT(0, "Invalid source");
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return 0;
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}
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/**
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* @brief get the pll source frequency
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*/
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__unused
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uint32_t get_pllsrc_frequency(void)
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{
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if (IS_ENABLED(STM32_PLL_SRC_HSI)) {
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return STM32_HSI_FREQ;
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} else if (IS_ENABLED(STM32_PLL_SRC_HSE)) {
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return STM32_HSE_FREQ;
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}
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__ASSERT(0, "Invalid source");
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return 0;
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}
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/**
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* @brief Set up pll configuration
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*/
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__unused
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void config_pll_sysclock(void)
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{
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LL_RCC_PLL_ConfigDomain_SYS(get_pll_source(),
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pllm(STM32_PLL_M_DIVISOR),
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STM32_PLL_N_MULTIPLIER,
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pllp(STM32_PLL_P_DIVISOR));
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}
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#endif /* defined(STM32_PLL_ENABLED) */
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/**
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* @brief Activate default clocks
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*/
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void config_enable_default_clocks(void)
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{
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/* Power Interface clock enabled by default */
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LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
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}
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