drivers: sdhc: imx_usdhc: add explicit fallthrough to I/O timing setup
DDR50/DDR52 modes should use PINCTRL_STATE_SLOW (50MHz), so the lack of a break statement after enabling DDR mode is expected. Add an explicit __fallthrough to resolve the issue flagged by coverity scan Fixes #65324 Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
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@ -404,6 +404,7 @@ static int imx_usdhc_set_io(const struct device *dev, struct sdhc_io *ios)
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case SDHC_TIMING_DDR52:
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/* Enable DDR mode */
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USDHC_EnableDDRMode(cfg->base, true, 0);
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__fallthrough;
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case SDHC_TIMING_SDR12:
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case SDHC_TIMING_SDR25:
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pinctrl_apply_state(cfg->pincfg, PINCTRL_STATE_SLOW);
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