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dts/riscv: add riscv compatible string where it's missing

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This commit adds the `riscv` compatible string to cpu nodes where it is
currently missing. This is convention is already followed by some cpu
nodes.

Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commit is contained in:
Filip Kokosinski 2024-01-16 13:53:22 +01:00 committed by Carles Cufí
parent 17670be2cc
commit 28c7674c66
9 changed files with 13 additions and 13 deletions
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2
dts/riscv/espressif/esp32c3/esp32c3_common.dtsi
View file

@ -31,7 +31,7 @@
cpu0: cpu@0 {
device_type = "cpu";
compatible = "espressif,riscv";
compatible = "espressif,riscv", "riscv";
riscv,isa = "rv32imc_zicsr";
reg = <0>;
cpu-power-states = <&light_sleep &deep_sleep>;

2
dts/riscv/gd/gd32vf103.dtsi
View file

@ -23,7 +23,7 @@
cpu: cpu@0 {
clock-frequency = <DT_FREQ_M(108)>;
compatible = "nuclei,bumblebee";
compatible = "nuclei,bumblebee", "riscv";
riscv,isa = "rv32imac_zicsr_zifencei";
reg = <0>;
};

2
dts/riscv/ite/it8xxx2.dtsi
View file

@ -28,7 +28,7 @@
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
compatible = "ite,riscv-ite";
compatible = "ite,riscv-ite", "riscv";
riscv,isa = "rv32imafc_zifencei";
device_type = "cpu";
reg = <0>;

2
dts/riscv/neorv32.dtsi
View file

@ -19,7 +19,7 @@
#size-cells = <0>;
cpu0: cpu@0 {
compatible = "neorv32-cpu";
compatible = "neorv32-cpu", "riscv";
riscv,isa = "rv32imc_zicsr";
reg = <0>;
device_type = "cpu";

2
dts/riscv/niosv/niosv-g.dtsi
View file

@ -17,7 +17,7 @@
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "intel,niosv";
compatible = "intel,niosv", "riscv";
riscv,isa = "rv32ima_zicsr_zifencei";
reg = <0>;
clock-frequency = <50000000>;

2
dts/riscv/niosv/niosv-m.dtsi
View file

@ -17,7 +17,7 @@
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "intel,niosv";
compatible = "intel,niosv", "riscv";
riscv,isa = "rv32ia_zicsr_zifencei";
reg = <0>;
clock-frequency = <50000000>;

2
dts/riscv/sifive/riscv32-fe310.dtsi
View file

@ -27,7 +27,7 @@
#address-cells = <1>;
#size-cells = <0>;
cpu: cpu@0 {
compatible = "sifive,e31";
compatible = "sifive,e31", "riscv";
device_type = "cpu";
reg = <0>;
riscv,isa = "rv32imac_zicsr_zifencei";

2
dts/riscv/sifive/riscv64-fu540.dtsi
View file

@ -33,7 +33,7 @@
#size-cells = <0>;
cpu: cpu@0 {
compatible = "sifive,e51";
compatible = "sifive,e51", "riscv";
device_type = "cpu";
reg = <0>;
riscv,isa = "rv64imac_zicsr_zifencei";

10
dts/riscv/sifive/riscv64-fu740.dtsi
View file

@ -32,7 +32,7 @@
#size-cells = <0>;
cpu0: cpu@0 {
compatible = "sifive,s7";
compatible = "sifive,s7", "riscv";
device_type = "cpu";
reg = <0>;
riscv,isa = "rv64imac_zicsr_zifencei";
@ -46,7 +46,7 @@
};
};
cpu1: cpu@1 {
compatible = "sifive,u74";
compatible = "sifive,u74", "riscv";
device_type = "cpu";
mmu-type = "riscv,sv39";
reg = <0x1>;
@ -59,7 +59,7 @@
};
};
cpu2: cpu@2 {
compatible = "sifive,u74";
compatible = "sifive,u74", "riscv";
device_type = "cpu";
mmu-type = "riscv,sv39";
reg = <0x2>;
@ -72,7 +72,7 @@
};
};
cpu3: cpu@3 {
compatible = "sifive,u74";
compatible = "sifive,u74", "riscv";
device_type = "cpu";
mmu-type = "riscv,sv39";
reg = <0x3>;
@ -85,7 +85,7 @@
};
};
cpu4: cpu@4 {
compatible = "sifive,u74";
compatible = "sifive,u74", "riscv";
device_type = "cpu";
mmu-type = "riscv,sv39";
reg = <0x4>;