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dts: bindings: fix typo in (retained_mem, rng, serial, spi)

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Utilize a code spell-checking tool to scan for and correct spelling errors
in all files within the dts/bindings/retained_mem, rng, serial and spi.

Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
This commit is contained in:
Pisit Sawangvonganan 2024-01-28 20:08:43 +07:00 committed by Anas Nashif
parent 22315d6a9d
commit 31a82699a8
6 changed files with 9 additions and 9 deletions
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2
dts/bindings/retained_mem/zephyr,retained-ram.yaml
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@ -1,7 +1,7 @@
# Copyright (c) 2023 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0
description: Unitialised RAM-based retained memory area.
description: Uninitialised RAM-based retained memory area.
compatible: "zephyr,retained-ram"

2
dts/bindings/rng/st,stm32-rng.yaml
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@ -18,7 +18,7 @@ properties:
the clock domain used, for instance:
<&rcc STM32_SRC_MSI CLK48_SEL(3)> /* RNG clock domain set to MSI */
A correctly configured domain clock is required to allow the integrated low
sampling clock detection mecanism to behave properly.
sampling clock detection mechanism to behave properly.
In provided example, MSI should be configured to provide 48Mhz clock.
nist-config:

2
dts/bindings/serial/infineon,xmc4xxx-uart.yaml
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@ -100,7 +100,7 @@ properties:
dma1 can connect to lines [8, 11].
2. For a given interrupt, calculate the service request (SR) number. Note the following
simple mapping: in USIC0 interrupt 84->SR0, interrupt 85->SR1, ... etc.
In USIC1, intterupt 90->SR0, 91->SR1, etc.
In USIC1, interrupt 90->SR0, 91->SR1, etc.
3. Select request_source from Table "DMA Request Source Selection" in XMC4XXX reference
manual.

4
dts/bindings/serial/st,stm32-uart-base.yaml
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@ -90,9 +90,9 @@ properties:
fifo-enable:
type: boolean
description: |
Enables transmit and receive FIFO using default FIFO confugration (typically threasholds
Enables transmit and receive FIFO using default FIFO configuration (typically thresholds
set to 1/8).
In TX, FIFO allows to work in burst mode, easing scheduling of loaded applications. It also
allows more reliable communication with UART devices sensitive to variation of inter-frames
delays.
In RX, FIFO reduces overrun occurences.
In RX, FIFO reduces overrun occurrences.

2
dts/bindings/spi/infineon,xmc4xxx-spi.yaml
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@ -55,7 +55,7 @@ properties:
dma1 can connect to lines [8, 11].
2. For a given interrupt, calculate the service request (SR) number. Note the following
simple mapping: in USIC0 interrupt 84->SR0, interrupt 85->SR1, ... etc.
In USIC1, intterupt 90->SR0, 91->SR1, etc.
In USIC1, interrupt 90->SR0, 91->SR1, etc.
3. Select request_source from Table "DMA Request Source Selection" in XMC4XXX reference
manual.

6
dts/bindings/spi/microchip,xec-qmspi-ldma.yaml
View file

@ -55,14 +55,14 @@ properties:
type: int
description: |
Delay in QMSPI main clocks from CS# assertion to first clock edge.
If not present use hardware default value. Refer to chip documention
If not present use hardware default value. Refer to chip documentation
for QMSPI input clock frequency.
dckcsoff:
type: int
description: |
Delay in QMSPI main clocks from last clock edge to CS# de-assertion.
If not present use hardware default value. Refer to chip documention
If not present use hardware default value. Refer to chip documentation
for QMSPI input clock frequency.
dldh:
@ -76,7 +76,7 @@ properties:
type: int
description: |
Delay in QMSPI main clocks from CS# de-assertion to CS# assertion.
If not present use hardware default value. Refer to chip documention
If not present use hardware default value. Refer to chip documentation
for QMSPI input clock frequency.
cs1-freq: