soc: smartbond: da1469x: Support Global Foundries silicon
Add support for the GF silicon variant. Signed-off-by: Ioannis Karachalios <ioannis.karachalios.px@renesas.com>
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@ -8,6 +8,12 @@
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#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
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#include <zephyr/linker/linker-defs.h>
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#include <string.h>
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#include <DA1469xAB.h>
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#include <da1469x_clock.h>
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#include <da1469x_otp.h>
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#include <da1469x_pd.h>
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#include <da1469x_pdc.h>
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#include <da1469x_trimv.h>
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#define REMAP_ADR0_QSPI 0x2
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@ -107,17 +113,47 @@ void z_arm_platform_init(void)
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#endif
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}
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static int renesas_da14699_init(void)
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static int renesas_da1469x_init(void)
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{
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/* Freeze watchdog until configured */
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GPREG->SET_FREEZE_REG = GPREG_SET_FREEZE_REG_FRZ_SYS_WDOG_Msk;
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/* Reset clock dividers to 0 */
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CRG_TOP->CLK_AMBA_REG &= ~(CRG_TOP_CLK_AMBA_REG_HCLK_DIV_Msk |
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CRG_TOP_CLK_AMBA_REG_PCLK_DIV_Msk);
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/* Enable all power domains except for radio */
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CRG_TOP->PMU_CTRL_REG = 0x02;
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CRG_TOP_CLK_AMBA_REG_PCLK_DIV_Msk);
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CRG_TOP->PMU_CTRL_REG |= (CRG_TOP_PMU_CTRL_REG_TIM_SLEEP_Msk |
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CRG_TOP_PMU_CTRL_REG_PERIPH_SLEEP_Msk |
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CRG_TOP_PMU_CTRL_REG_COM_SLEEP_Msk |
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CRG_TOP_PMU_CTRL_REG_RADIO_SLEEP_Msk);
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/* PDC should take care of PD_SYS */
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CRG_TOP->PMU_CTRL_REG &= ~CRG_TOP_PMU_CTRL_REG_SYS_SLEEP_Msk;
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/*
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* Due to crosstalk issues any power rail can potentially
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* issue a fake event. This is typically observed upon
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* switching power sources, that is DCDC <--> LDOs <--> Retention LDOs.
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*/
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CRG_TOP->BOD_CTRL_REG &= ~(CRG_TOP_BOD_CTRL_REG_BOD_V14_EN_Msk |
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CRG_TOP_BOD_CTRL_REG_BOD_V18F_EN_Msk |
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CRG_TOP_BOD_CTRL_REG_BOD_VDD_EN_Msk |
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CRG_TOP_BOD_CTRL_REG_BOD_V18P_EN_Msk |
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CRG_TOP_BOD_CTRL_REG_BOD_V18_EN_Msk |
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CRG_TOP_BOD_CTRL_REG_BOD_V30_EN_Msk |
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CRG_TOP_BOD_CTRL_REG_BOD_VBAT_EN_Msk);
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da1469x_pdc_reset();
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da1469x_otp_init();
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da1469x_trimv_init_from_otp();
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da1469x_pd_init();
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da1469x_pd_acquire(MCU_PD_DOMAIN_SYS);
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da1469x_pd_acquire(MCU_PD_DOMAIN_TIM);
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da1469x_pd_acquire(MCU_PD_DOMAIN_COM);
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return 0;
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}
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SYS_INIT(renesas_da14699_init, PRE_KERNEL_1, 0);
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SYS_INIT(renesas_da1469x_init, PRE_KERNEL_1, 0);
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