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soc: riscv: remove empty soc.h files

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Because they're just not needed.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
This commit is contained in:
Gerard Marull-Paretas 2024-01-16 15:41:14 +01:00 committed by Fabio Baltieri
parent e7cc2fafb4
commit 48dbcf5479
10 changed files with 0 additions and 116 deletions
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14
soc/riscv/andes_v5/ae350/soc.h
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@ -1,14 +0,0 @@
/*
* Copyright (c) 2021 Andes Technology Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @brief Macros for the Andes AE350 platform
*/
#ifndef __RISCV_ANDES_AE350_SOC_H_
#define __RISCV_ANDES_AE350_SOC_H_
#endif /* __RISCV_ANDES_AE350_SOC_H_ */

17
soc/riscv/efinix_sapphire/soc.h
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@ -1,17 +0,0 @@
/*
* Copyright (c) 2023 Efinix Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef __RISCV32_EFINIX_SAPPHIRE_SOC_H_
#define __RISCV32_EFINIX_SAPPHIRE_SOC_H_
#include <zephyr/arch/riscv/sys_io.h>
#include <zephyr/devicetree.h>
#ifndef _ASMLANGUAGE
#endif /* _ASMLANGUAGE */
#endif /* __RISCV32_EFINIX_SAPPHIRE_SOC_H_ */

14
soc/riscv/gd_gd32/gd32vf103/soc.h
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@ -1,14 +0,0 @@
/*
* Copyright (c) 2021 Tokita, Hiroshi <tokita.hiroshi@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file SoC configuration macros for the GigaDevice GD32VF103 processor
*/
#ifndef RISCV_GD32VF103_SOC_H_
#define RISCV_GD32VF103_SOC_H_
#endif /* RISCV_GD32VF103_SOC_H */

12
soc/riscv/intel_niosv/niosv/soc.h
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@ -1,12 +0,0 @@
/*
* Copyright (C) 2023, Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef RISCV_INTEL_FPGA_NIOSV_H
#define RISCV_INTEL_FPGA_NIOSV_H
#include <zephyr/devicetree.h>
#endif /* RISCV_INTEL_FPGA_NIOSV_H */

8
soc/riscv/microchip_miv/miv/soc.h
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@ -1,8 +0,0 @@
/*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef __RISCV32_MIV_SOC_H_
#define __RISCV32_MIV_SOC_H_
#endif /* __RISCV32_MIV_SOC_H_ */

11
soc/riscv/microchip_miv/polarfire/soc.h
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@ -1,11 +0,0 @@
/*
* SPDX-License-Identifier: Apache-2.0
*
* Copyright (c) 2020-2021 Microchip Technology Inc
*/
#ifndef __RISCV64_MPFS_SOC_H_
#define __RISCV64_MPFS_SOC_H_
#include <zephyr/devicetree.h>
#endif /* __RISCV64_MPFS_SOC_H_ */

10
soc/riscv/opentitan/soc.h
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@ -1,10 +0,0 @@
/*
* Copyright (c) 2023 Rivos Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef __RISCV_OPENTITAN_SOC_H_
#define __RISCV_OPENTITAN_SOC_H_
#endif /* __RISCV_OPENTITAN_SOC_H_ */

10
soc/riscv/renode_virt/soc.h
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@ -1,10 +0,0 @@
/*
* Copyright (c) 2023 Meta
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef __RISCV32_RENODE_SOC_H_
#define __RISCV32_RENODE_SOC_H_
#endif /* __RISCV32_RENODE_SOC_H_ */

10
soc/riscv/starfive_jh71xx/jh71xx/soc.h
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@ -1,10 +0,0 @@
/*
* Copyright (c) 2020 Cobham Gaisler AB
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef __RISCV_VIRT_SOC_H_
#define __RISCV_VIRT_SOC_H_
#endif

10
soc/riscv/virt/soc.h
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@ -1,10 +0,0 @@
/*
* Copyright (c) 2020 Cobham Gaisler AB
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef __RISCV_VIRT_SOC_H_
#define __RISCV_VIRT_SOC_H_
#endif