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dts: bindings: gd32-dma-base: add gd,mem2mem property

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Add `gd,mem2mem` property to indicate the DMA controller supports
memory to memory transfer.

Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
This commit is contained in:
TOKITA Hiroshi 2022-12-10 17:13:51 +09:00 committed by Carles Cufí
parent 59044c6d63
commit 498ef65242
6 changed files with 20 additions and 1 deletions
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9
drivers/dma/dma_gd32.c
View file

@ -58,6 +58,7 @@ struct dma_gd32_config {
uint32_t reg; uint32_t reg;
uint32_t channels; uint32_t channels;
uint16_t clkid; uint16_t clkid;
bool mem2mem;
#ifdef CONFIG_SOC_SERIES_GD32F4XX #ifdef CONFIG_SOC_SERIES_GD32F4XX
struct reset_dt_spec reset; struct reset_dt_spec reset;
#endif #endif
@ -403,6 +404,11 @@ static int dma_gd32_config(const struct device *dev, uint32_t channel,
return -ENOTSUP; return -ENOTSUP;
} }
if (dma_cfg->channel_direction == MEMORY_TO_MEMORY && !cfg->mem2mem) {
LOG_ERR("not supporting MEMORY_TO_MEMORY");
return -ENOTSUP;
}
#ifdef CONFIG_SOC_SERIES_GD32F4XX #ifdef CONFIG_SOC_SERIES_GD32F4XX
if (dma_cfg->dma_slot > 0xF) { if (dma_cfg->dma_slot > 0xF) {
LOG_ERR("dma_slot must be <7 (%" PRIu32 ")", LOG_ERR("dma_slot must be <7 (%" PRIu32 ")",
@ -665,10 +671,11 @@ static const struct dma_driver_api dma_gd32_driver_api = {
} \ } \
static const struct dma_gd32_config dma_gd32##inst##_config = { \ static const struct dma_gd32_config dma_gd32##inst##_config = { \
.reg = DT_INST_REG_ADDR(inst), \ .reg = DT_INST_REG_ADDR(inst), \
.channels = DT_INST_PROP(inst, dma_channels), \
.clkid = DT_INST_CLOCKS_CELL(inst, id), \ .clkid = DT_INST_CLOCKS_CELL(inst, id), \
.mem2mem = DT_INST_PROP(inst, gd_mem2mem), \
IF_ENABLED(CONFIG_SOC_SERIES_GD32F4XX, \ IF_ENABLED(CONFIG_SOC_SERIES_GD32F4XX, \
(.reset = RESET_DT_SPEC_INST_GET(inst),)) \ (.reset = RESET_DT_SPEC_INST_GET(inst),)) \
.channels = DT_INST_PROP(inst, dma_channels), \
.irq_configure = dma_gd32##inst##_irq_configure, \ .irq_configure = dma_gd32##inst##_irq_configure, \
}; \ }; \
\ \

2
dts/arm/gigadevice/gd32e50x/gd32e50x.dtsi
View file

@ -411,6 +411,7 @@
<15 0>, <16 0>, <17 0>; <15 0>, <16 0>, <17 0>;
clocks = <&cctl GD32_CLOCK_DMA0>; clocks = <&cctl GD32_CLOCK_DMA0>;
dma-channels = <7>; dma-channels = <7>;
gd,mem2mem;
#dma-cells = <2>; #dma-cells = <2>;
status = "disabled"; status = "disabled";
}; };
@ -422,6 +423,7 @@
<60 0>; <60 0>;
clocks = <&cctl GD32_CLOCK_DMA1>; clocks = <&cctl GD32_CLOCK_DMA1>;
dma-channels = <5>; dma-channels = <5>;
gd,mem2mem;
#dma-cells = <2>; #dma-cells = <2>;
status = "disabled"; status = "disabled";
}; };

2
dts/arm/gigadevice/gd32f403/gd32f403.dtsi
View file

@ -496,6 +496,7 @@
<15 0>, <16 0>, <17 0>; <15 0>, <16 0>, <17 0>;
clocks = <&cctl GD32_CLOCK_DMA0>; clocks = <&cctl GD32_CLOCK_DMA0>;
dma-channels = <7>; dma-channels = <7>;
gd,mem2mem;
#dma-cells = <2>; #dma-cells = <2>;
status = "disabled"; status = "disabled";
}; };
@ -507,6 +508,7 @@
<60 0>; <60 0>;
clocks = <&cctl GD32_CLOCK_DMA1>; clocks = <&cctl GD32_CLOCK_DMA1>;
dma-channels = <5>; dma-channels = <5>;
gd,mem2mem;
#dma-cells = <2>; #dma-cells = <2>;
status = "disabled"; status = "disabled";
}; };

2
dts/arm/gigadevice/gd32f4xx/gd32f4xx.dtsi
View file

@ -625,6 +625,7 @@
clocks = <&cctl GD32_CLOCK_DMA0>; clocks = <&cctl GD32_CLOCK_DMA0>;
resets = <&rctl GD32_RESET_DMA0>; resets = <&rctl GD32_RESET_DMA0>;
dma-channels = <8>; dma-channels = <8>;
gd,mem2mem;
#dma-cells = <2>; #dma-cells = <2>;
status = "disabled"; status = "disabled";
}; };
@ -637,6 +638,7 @@
clocks = <&cctl GD32_CLOCK_DMA1>; clocks = <&cctl GD32_CLOCK_DMA1>;
resets = <&rctl GD32_RESET_DMA1>; resets = <&rctl GD32_RESET_DMA1>;
dma-channels = <8>; dma-channels = <8>;
gd,mem2mem;
#dma-cells = <2>; #dma-cells = <2>;
status = "disabled"; status = "disabled";
}; };

4
dts/bindings/dma/gd,gd32-dma-base.yaml
View file

@ -15,3 +15,7 @@ properties:
clocks: clocks:
required: true required: true
gd,mem2mem:
type: boolean
description: The DMA controller supporting memory to memory transfer

2
dts/riscv/gigadevice/gd32vf103.dtsi
View file

@ -392,6 +392,7 @@
<34 0>, <35 0>, <36 0>; <34 0>, <35 0>, <36 0>;
clocks = <&cctl GD32_CLOCK_DMA0>; clocks = <&cctl GD32_CLOCK_DMA0>;
dma-channels = <7>; dma-channels = <7>;
gd,mem2mem;
#dma-cells = <2>; #dma-cells = <2>;
status = "disabled"; status = "disabled";
}; };
@ -403,6 +404,7 @@
<79 0>; <79 0>;
clocks = <&cctl GD32_CLOCK_DMA1>; clocks = <&cctl GD32_CLOCK_DMA1>;
dma-channels = <5>; dma-channels = <5>;
gd,mem2mem;
#dma-cells = <2>; #dma-cells = <2>;
status = "disabled"; status = "disabled";
}; };