dts: arm: Add base DTS support for STM32 Nucleo board
This patch adds the base DTS and yaml files required to support DTS for the STM32L476 based Nucleo board. Change-Id: Ic606a895a25f27d2990f651d0f3c3c5d84818cfd Signed-off-by: Andy Gross <andy.gross@linaro.org>
This commit is contained in:
Erwan Gouriou
Anas Nashif
parent
b465fbe312
commit
52bca037be
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@ -2,5 +2,6 @@ ifeq ($(CONFIG_HAS_DTS),y)
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dtb-$(CONFIG_BOARD_FRDM_K64F) = frdm_k64f.dts_compiled
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dtb-$(CONFIG_BOARD_HEXIWEAR_K64) = hexiwear_k64.dts_compiled
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dtb-$(CONFIG_BOARD_CC3200_LAUNCHXL) = cc3200_launchxl.dts_compiled
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dtb-$(CONFIG_BOARD_NUCLEO_L476RG) = nucleo_l476rg.dts_compiled
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always := $(dtb-y)
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endif
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75
dts/arm/nucleo_l476rg.dts
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75
dts/arm/nucleo_l476rg.dts
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@ -0,0 +1,75 @@
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/*
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* Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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/dts-v1/;
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#include "stm32l476.dtsi"
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/ {
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model = "STMicroelectronics STM32L476RG-NUCLEO board";
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compatible = "st,stm32l476rg-nucleo", "st,stm32l476";
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chosen {
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zephyr,console = &usart2;
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zephyr,sram = &sram0;
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zephyr,flash = &flash0;
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};
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leds {
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compatible = "gpio-leds";
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red {
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gpios = <&gpiog 14 0>;
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};
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green {
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gpios = <&gpiog 13 0>;
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linux,default-trigger = "heartbeat";
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};
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};
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};
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&clk_hse {
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clock-frequency = <8000000>;
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};
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&usart2 {
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status = "ok";
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};
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9
dts/arm/nucleo_l476rg.fixup
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9
dts/arm/nucleo_l476rg.fixup
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@ -0,0 +1,9 @@
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/* This file is a temporary workaround for mapping of the generated information
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* to the current driver definitions. This will be removed when the drivers
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* are modified to handle the generated information, or the mapping of
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* generated data matches the driver definitions.
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*/
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#define CONFIG_NUM_IRQS ARM_ARMV7M_NVIC_E000E100_NUM_IRQS
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#define CONFIG_NUM_IRQ_PRIO_BITS ARM_ARMV7M_NVIC_E000E100_NUM_IRQ_PRIO_BITS
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158
dts/arm/stm32l476.dtsi
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158
dts/arm/stm32l476.dtsi
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@ -0,0 +1,158 @@
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/*
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* Copyright (c) 2016 Linaro Limited.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include "armv7-m.dtsi"
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/ {
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sram0: memory {
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reg = <0x20000000 0x18000>;
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};
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flash0: flash {
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reg = <0x08000000 0x100000>;
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};
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clocks {
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clk_hse: clk-hse {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <0>;
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};
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};
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soc {
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usart1: uart@40013800 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40013800 0x400>;
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interrupts = <37>;
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zephyr,irq-prio = <0>;
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baud-rate = <115200>;
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status = "disabled";
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};
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usart2: uart@40004400 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40004400 0x400>;
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interrupts = <38>;
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zephyr,irq-prio = <0>;
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baud-rate = <115200>;
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status = "disabled";
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};
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usart3: uart@40004800 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40004800 0x400>;
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interrupts = <39>;
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zephyr,irq-prio = <0>;
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baud-rate = <115200>;
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status = "disabled";
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};
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uart4: uart@40004c00 {
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compatible = "st,stm32-uart";
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reg = <0x40004c00 0x400>;
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interrupts = <52>;
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zephyr,irq-prio = <0>;
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baud-rate = <115200>;
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status = "disabled";
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};
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uart5: uart@40005000 {
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compatible = "st,stm32-uart";
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reg = <0x40005000 0x400>;
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interrupts = <53>;
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zephyr,irq-prio = <0>;
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baud-rate = <115200>;
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status = "disabled";
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};
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syscfg: system-config@40010000 {
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compatible = "syscon";
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reg = <0x40013800 0x400>;
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};
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pin-controller {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "st,stm32l4xx-pinctrl";
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ranges = <0 0x48000000 0x2000>;
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pins-are-numbered;
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gpioa: gpio@48000000 {
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x0 0x400>;
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st,bank-name = "GPIOA";
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};
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gpiob: gpio@48000400 {
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x400 0x400>;
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st,bank-name = "GPIOB";
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};
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gpioc: gpio@48000800 {
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x800 0x400>;
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st,bank-name = "GPIOC";
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};
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gpiod: gpio@48000c00 {
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0xc00 0x400>;
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st,bank-name = "GPIOD";
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};
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gpioe: gpio@48001000 {
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x1000 0x400>;
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st,bank-name = "GPIOE";
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};
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gpiof: gpio@48001400 {
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x1400 0x400>;
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st,bank-name = "GPIOF";
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};
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gpiog: gpio@48001800 {
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x1800 0x400>;
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st,bank-name = "GPIOG";
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};
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gpioh: gpio@48001c00 {
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x1c00 0x400>;
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st,bank-name = "GPIOH";
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};
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};
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};
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};
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&nvic {
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num-irq-prio-bits = <4>;
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num-irqs = <82>;
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};
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37
dts/arm/yaml/st,stm32-usart.yaml
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37
dts/arm/yaml/st,stm32-usart.yaml
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@ -0,0 +1,37 @@
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---
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title: STM32 USART
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id: st,stm32-usart
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version: 0.1
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description: >
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This binding gives a base representation of the STM32 USART
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inherits:
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- !include uart.yaml
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- !include zephyr_devices.yaml
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properties:
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- compatible:
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type: string
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category: required
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description: compatible strings
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constraint: "st,stm32-usart"
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- reg:
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type: array
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description: mmio register space
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generation: define
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category: required
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- interrupts:
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type: array
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category: required
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description: required interrupts
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generation: define
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- clocks:
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type: array
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category: required
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description: Clock gate control information
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generation: define
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...
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