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arch: em{7,9,11}d: Add dts support

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Add initial device tree support for the em{7,9,11}d SoC and associated
em_starterkit boards.  The device tree at this point specifies cpu core,
memory, interrupt controller, uart's and i2c controllers.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
Kumar Gala 2018-03-14 16:36:09 -05:00 committed by ruuddw
parent 22eeb70a26
commit 60ec8be309
19 changed files with 278 additions and 76 deletions
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25
arch/arc/soc/em11d/Kconfig.defconfig
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@ -29,31 +29,6 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC
config HARVARD
def_bool n
config FLASH_BASE_ADDRESS
default 0x00000000
config FLASH_SIZE
default 0
# em11d has no FLASH so size is 0.
config SRAM_BASE_ADDRESS
default 0x10000000
config SRAM_SIZE
default 131072
config ICCM_BASE_ADDRESS
default 0x00000000
config ICCM_SIZE
default 64
config DCCM_BASE_ADDRESS
default 0x80000000
config DCCM_SIZE
default 64
config CACHE_FLUSHING
def_bool y

9
arch/arc/soc/em11d/dts.fixup Normal file
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@ -0,0 +1,9 @@
/* SoC level DTS fixup file */
#define CONFIG_DCCM_BASE_ADDRESS ARC_DCCM_80000000_BASE_ADDRESS
#define CONFIG_DCCM_SIZE (ARC_DCCM_80000000_SIZE >> 10)
#define CONFIG_ICCM_BASE_ADDRESS ARC_ICCM_0_BASE_ADDRESS
#define CONFIG_ICCM_SIZE (ARC_ICCM_0_SIZE >> 10)
/* End of SoC Level DTS fixup file */

1
arch/arc/soc/em11d/linker.ld
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@ -29,4 +29,5 @@
#define DCCM_START CONFIG_DCCM_BASE_ADDRESS
#define DCCM_SIZE CONFIG_DCCM_SIZE
#include <generated_dts_board.h>
#include <arch/arc/v2/linker.ld>

25
arch/arc/soc/em7d/Kconfig.defconfig
View file

@ -38,31 +38,6 @@ config ARC_FIRQ
def_bool n if BOARD_EM_STARTERKIT_R23
def_bool y if BOARD_EM_STARTERKIT_R22
config FLASH_BASE_ADDRESS
default 0x00000000
config FLASH_SIZE
default 0
# em7d has no FLASH so size is 0.
config SRAM_BASE_ADDRESS
default 0x10000000
config SRAM_SIZE
default 131072
config ICCM_BASE_ADDRESS
default 0x00000000
config ICCM_SIZE
default 256
config DCCM_BASE_ADDRESS
default 0x80000000
config DCCM_SIZE
default 128
config CACHE_FLUSHING
def_bool y

9
arch/arc/soc/em7d/dts.fixup Normal file
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@ -0,0 +1,9 @@
/* SoC level DTS fixup file */
#define CONFIG_DCCM_BASE_ADDRESS ARC_DCCM_80000000_BASE_ADDRESS
#define CONFIG_DCCM_SIZE (ARC_DCCM_80000000_SIZE >> 10)
#define CONFIG_ICCM_BASE_ADDRESS ARC_ICCM_0_BASE_ADDRESS
#define CONFIG_ICCM_SIZE (ARC_ICCM_0_SIZE >> 10)
/* End of SoC Level DTS fixup file */

1
arch/arc/soc/em7d/linker.ld
View file

@ -29,4 +29,5 @@
#define DCCM_START CONFIG_DCCM_BASE_ADDRESS
#define DCCM_SIZE CONFIG_DCCM_SIZE
#include <generated_dts_board.h>
#include <arch/arc/v2/linker.ld>

26
arch/arc/soc/em9d/Kconfig.defconfig
View file

@ -29,30 +29,4 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC
config HARVARD
def_bool y
config FLASH_BASE_ADDRESS
default 0x00000000
config FLASH_SIZE
default 0
# em9d has no FLASH so size is 0.
config SRAM_BASE_ADDRESS
default 0x00000000
config SRAM_SIZE
default 0
# em9d has no SRAM so size is 0.
config ICCM_BASE_ADDRESS
default 0x00000000
config ICCM_SIZE
default 256
config DCCM_BASE_ADDRESS
default 0x80000000
config DCCM_SIZE
default 128
endif #SOC_EM9D

12
arch/arc/soc/em9d/dts.fixup Normal file
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@ -0,0 +1,12 @@
/* SoC level DTS fixup file */
#define CONFIG_DCCM_BASE_ADDRESS ARC_DCCM_80000000_BASE_ADDRESS
#define CONFIG_DCCM_SIZE (ARC_DCCM_80000000_SIZE >> 10)
#define CONFIG_ICCM_BASE_ADDRESS ARC_ICCM_0_BASE_ADDRESS
#define CONFIG_ICCM_SIZE (ARC_ICCM_0_SIZE >> 10)
#define CONFIG_SRAM_SIZE 0
#define CONFIG_SRAM_BASE_ADDRESS 0
/* End of SoC Level DTS fixup file */

1
arch/arc/soc/em9d/linker.ld
View file

@ -26,5 +26,6 @@
#define DCCM_START CONFIG_DCCM_BASE_ADDRESS
#define DCCM_SIZE CONFIG_DCCM_SIZE
#include <generated_dts_board.h>
#include <arch/arc/v2/linker.ld>

1
boards/arc/em_starterkit/Kconfig.board
View file

@ -7,6 +7,7 @@
config BOARD_EM_STARTERKIT
bool "ARC EM Starter Kit"
depends on (SOC_EM7D || SOC_EM9D || SOC_EM11D)
select HAS_DTS
help
The DesignWare ARC EM Starter Kit board is a board
that can host up to 3 different SOC FPGA bit files.

1
boards/arc/em_starterkit/arc_mpu_regions.c
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@ -4,6 +4,7 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include <generated_dts_board.h>
#include <soc.h>
#include <arch/arc/v2/mpu/arc_mpu.h>
#include <linker/linker-defs.h>

23
boards/arc/em_starterkit/em_starterkit.dts Normal file
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@ -0,0 +1,23 @@
/dts-v1/;
#include <em9d.dtsi>
/ {
model = "em_starterkit-em9d";
compatible = "snps,em_starterkit-em9d", "snps,em_starterkit";
aliases {
uart_0 = &uart0;
uart_1 = &uart1;
uart_2 = &uart2;
};
chosen {
zephyr,console = &uart1;
};
};
&uart1 {
status = "ok";
current-speed = <115200>;
};

24
boards/arc/em_starterkit/em_starterkit_em11d.dts Normal file
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@ -0,0 +1,24 @@
/dts-v1/;
#include <em11d.dtsi>
/ {
model = "em_starterkit-em11d";
compatible = "snps,em_starterkit-em11d", "snps,em_starterkit";
aliases {
uart_0 = &uart0;
uart_1 = &uart1;
uart_2 = &uart2;
};
chosen {
zephyr,sram = &sram0;
zephyr,console = &uart1;
};
};
&uart1 {
status = "ok";
current-speed = <115200>;
};

24
boards/arc/em_starterkit/em_starterkit_em7d.dts Normal file
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@ -0,0 +1,24 @@
/dts-v1/;
#include <em7d.dtsi>
/ {
model = "em_starterkit-em7";
compatible = "snps,em_starterkit-em7d", "snps,em_starterkit";
aliases {
uart_0 = &uart0;
uart_1 = &uart1;
uart_2 = &uart2;
};
chosen {
zephyr,sram = &sram0;
zephyr,console = &uart1;
};
};
&uart1 {
status = "ok";
current-speed = <115200>;
};

1
boards/arc/em_starterkit/em_starterkit_em7d_v22.dts Normal file
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@ -0,0 +1 @@
#include "em_starterkit_em7d.dts"

38
dts/arc/em11d.dtsi Normal file
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@ -0,0 +1,38 @@
#include <emsk.dtsi>
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "snps,arcem11d";
reg = <1>;
};
intc: arcv2-intc@0 {
compatible = "snps,arcv2-intc";
interrupt-controller;
#interrupt-cells = <2>;
};
};
iccm0: iccm@0 {
device_type = "memory";
compatible = "arc,iccm";
reg = <0x0 0x10000>;
};
sram0: memory@10000000 {
device_type = "memory";
compatible = "mmio-sram";
reg = <0x10000000 0x8000000>;
};
dccm0: dccm@80000000 {
device_type = "memory";
compatible = "arc,dccm";
reg = <0x80000000 0x10000>;
};
};

38
dts/arc/em7d.dtsi Normal file
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@ -0,0 +1,38 @@
#include <emsk.dtsi>
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "snps,arcem7d";
reg = <1>;
};
intc: arcv2-intc@0 {
compatible = "snps,arcv2-intc";
interrupt-controller;
#interrupt-cells = <2>;
};
};
iccm0: iccm@0 {
device_type = "memory";
compatible = "arc,iccm";
reg = <0x0 0x40000>;
};
sram0: memory@10000000 {
device_type = "memory";
compatible = "mmio-sram";
reg = <0x10000000 0x8000000>;
};
dccm0: dccm@80000000 {
device_type = "memory";
compatible = "arc,dccm";
reg = <0x80000000 0x20000>;
};
};

32
dts/arc/em9d.dtsi Normal file
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@ -0,0 +1,32 @@
#include <emsk.dtsi>
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "snps,arcem9d";
reg = <1>;
};
intc: arcv2-intc@0 {
compatible = "snps,arcv2-intc";
interrupt-controller;
#interrupt-cells = <2>;
};
};
iccm0: iccm@0 {
device_type = "memory";
compatible = "arc,iccm";
reg = <0x0 0x40000>;
};
dccm0: dccm@80000000 {
device_type = "memory";
compatible = "arc,dccm";
reg = <0x80000000 0x20000>;
};
};

63
dts/arc/emsk.dtsi Normal file
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@ -0,0 +1,63 @@
#include "skeleton.dtsi"
#include <dt-bindings/i2c/i2c.h>
/ {
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges;
i2c0: i2c@f0004000 {
compatible = "snps,designware-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0xf0004000 0x1000>;
label = "I2C_0";
interrupts = <25 1>;
interrupt-parent = <&intc>;
};
i2c1: i2c@f0005000 {
compatible = "snps,designware-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0xf0005000 0x1000>;
label = "I2C_1";
interrupts = <26 1>;
interrupt-parent = <&intc>;
};
uart0: uart@f0008000 {
compatible = "ns16550";
reg = <0xf0008000 0x1000>;
label = "UART_0";
interrupts = <29 1>;
interrupt-parent = <&intc>;
status = "disabled";
};
uart1: uart@f0009000 {
compatible = "ns16550";
reg = <0xf0009000 0x1000>;
label = "UART_1";
interrupts = <30 1>;
interrupt-parent = <&intc>;
status = "disabled";
};
uart2: uart@f000a000 {
compatible = "ns16550";
reg = <0xf000a000 0x1000>;
label = "UART_2";
interrupts = <31 1>;
interrupt-parent = <&intc>;
status = "disabled";
};
};
};