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arch: arm: cortex_m: Use cmsis api instead of inline asm in arch_irq_*

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Asm is notoriously harder to maintain than C and requires core specific
adaptation which impairs even more the readability of the code.

Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
This commit is contained in:
Wilfried Chauveau 2024-01-24 12:02:13 +00:00 committed by Carles Cufí
parent 8e55468af2
commit 72312feead
1 changed files with 11 additions and 26 deletions
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37
include/zephyr/arch/arm/asm_inline_gcc.h
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@ -21,6 +21,7 @@
#include <zephyr/toolchain.h> #include <zephyr/toolchain.h>
#include <zephyr/types.h> #include <zephyr/types.h>
#include <zephyr/arch/arm/exception.h> #include <zephyr/arch/arm/exception.h>
#include <cmsis_core.h>
#if defined(CONFIG_CPU_AARCH32_CORTEX_R) || defined(CONFIG_CPU_AARCH32_CORTEX_A) #if defined(CONFIG_CPU_AARCH32_CORTEX_R) || defined(CONFIG_CPU_AARCH32_CORTEX_A)
#include <zephyr/arch/arm/cortex_a_r/cpu.h> #include <zephyr/arch/arm/cortex_a_r/cpu.h>
@ -46,25 +47,15 @@ static ALWAYS_INLINE unsigned int arch_irq_lock(void)
#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) #if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
#if CONFIG_MP_MAX_NUM_CPUS == 1 || defined(CONFIG_ARMV8_M_BASELINE) #if CONFIG_MP_MAX_NUM_CPUS == 1 || defined(CONFIG_ARMV8_M_BASELINE)
__asm__ volatile("mrs %0, PRIMASK;" key = __get_PRIMASK();
"cpsid i" __disable_irq();
: "=r" (key)
:
: "memory");
#else #else
#error "Cortex-M0 and Cortex-M0+ require SoC specific support for cross core synchronisation." #error "Cortex-M0 and Cortex-M0+ require SoC specific support for cross core synchronisation."
#endif #endif
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE) #elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
unsigned int tmp; key = __get_BASEPRI();
__set_BASEPRI_MAX(_EXC_IRQ_DEFAULT_PRIO);
__asm__ volatile( __ISB();
"mov %1, %2;"
"mrs %0, BASEPRI;"
"msr BASEPRI_MAX, %1;"
"isb;"
: "=r"(key), "=r"(tmp)
: "i"(_EXC_IRQ_DEFAULT_PRIO)
: "memory");
#elif defined(CONFIG_ARMV7_R) || defined(CONFIG_AARCH32_ARMV8_R) \ #elif defined(CONFIG_ARMV7_R) || defined(CONFIG_AARCH32_ARMV8_R) \
|| defined(CONFIG_ARMV7_A) || defined(CONFIG_ARMV7_A)
__asm__ volatile( __asm__ volatile(
@ -92,23 +83,17 @@ static ALWAYS_INLINE void arch_irq_unlock(unsigned int key)
if (key != 0U) { if (key != 0U) {
return; return;
} }
__asm__ volatile( __enable_irq();
"cpsie i;" __ISB();
"isb"
: : : "memory");
#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE) #elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
__asm__ volatile( __set_BASEPRI(key);
"msr BASEPRI, %0;" __ISB();
"isb;"
: : "r"(key) : "memory");
#elif defined(CONFIG_ARMV7_R) || defined(CONFIG_AARCH32_ARMV8_R) \ #elif defined(CONFIG_ARMV7_R) || defined(CONFIG_AARCH32_ARMV8_R) \
|| defined(CONFIG_ARMV7_A) || defined(CONFIG_ARMV7_A)
if (key != 0U) { if (key != 0U) {
return; return;
} }
__asm__ volatile( __enable_irq();
"cpsie i;"
: : : "memory", "cc");
#else #else
#error Unknown ARM architecture #error Unknown ARM architecture
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */ #endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */