soc: brcm: add support for BCM2712

Add support for BCM2712, SoC of Raspberry Pi 5.

Signed-off-by: Junho Lee <junho@tsnlab.com>

dts/arm64/broadcom/bcm2712.dtsi

@@ -0,0 +1,71 @@
+/*
+ * Copyright 2024 Myeonghyeon Park <myeonghyeon@tsnlab.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm64/armv8-a.dtsi>
+#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a76";
+			reg = <0>;
+		};
+	};
+
+	interrupt-parent = <&gic>;
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL
+			      IRQ_DEFAULT_PRIORITY>,
+			     <GIC_PPI 14 IRQ_TYPE_LEVEL
+			      IRQ_DEFAULT_PRIORITY>,
+			     <GIC_PPI 11 IRQ_TYPE_LEVEL
+			      IRQ_DEFAULT_PRIORITY>,
+			     <GIC_PPI 10 IRQ_TYPE_LEVEL
+			      IRQ_DEFAULT_PRIORITY>;
+	};
+
+	soc {
+		#address-cells = <2>;
+		#size-cells = <1>;
+
+		sram0: memory@200000 {
+			device_type = "memory";
+			compatible = "mmio-sram";
+			reg = <0x0 0x200000 0x80000>;
+		};
+
+		gic: interrupt-controller@107fff9000 {
+			compatible = "arm,gic-v2", "arm,gic";
+			reg = <0x10 0x7fff9000 0x1000>,
+			      <0x10 0x7fffa000 0x2000>;
+			interrupt-controller;
+			#interrupt-cells = <4>;
+			status = "okay";
+		};
+
+		gpio2@107d517c00 {
+			compatible = "simple-bus";
+			reg = <0x10 0x7d517c00 0x40>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+			gio_aon: gpio@0 {
+				compatible = "brcm,brcmstb-gpio";
+				reg = <0>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				ngpios = <17>;
+				status = "disabled";
+			};
+		};
+	};
+};

soc/brcm/bcm2712/CMakeLists.txt

@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: Apache-2.0
+zephyr_sources_ifdef(CONFIG_ARM_MMU mmu_regions.c)
+
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm64/scripts/linker.ld CACHE INTERNAL "")

soc/brcm/bcm2712/Kconfig

@@ -0,0 +1,7 @@
+# Copyright 2024 Junho Lee <junho@tsnlab.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_BCM2712
+	select ARM64
+	select CPU_CORTEX_A76
+	select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS

soc/brcm/bcm2712/Kconfig.defconfig

@@ -0,0 +1,14 @@
+# Copyright 2024 Junho Lee <junho@tsnlab.com>
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_BCM2712
+
+config NUM_IRQS
+	int
+	default 280
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	int
+	default 54000000
+
+endif

soc/brcm/bcm2712/Kconfig.soc

@@ -0,0 +1,8 @@
+# Copyright 2024 Junho Lee <junho@tsnlab.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_BCM2712
+	bool
+
+config SOC
+	default "bcm2712" if SOC_BCM2712

soc/brcm/bcm2712/mmu_regions.c

@@ -0,0 +1,26 @@
+/*
+ * Copyright 2024 Junho Lee <junho@tsnlab.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/arch/arm64/arm_mmu.h>
+#include <zephyr/devicetree.h>
+#include <zephyr/sys/util.h>
+
+static const struct arm_mmu_region mmu_regions[] = {
+	MMU_REGION_FLAT_ENTRY("GIC",
+			      DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 0),
+			      DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 0),
+			      MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_DEFAULT_SECURE_STATE),
+
+	MMU_REGION_FLAT_ENTRY("GIC",
+			      DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 1),
+			      DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 1),
+			      MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_DEFAULT_SECURE_STATE),
+};
+
+const struct arm_mmu_config mmu_config = {
+	.num_regions = ARRAY_SIZE(mmu_regions),
+	.mmu_regions = mmu_regions,
+};

soc/brcm/bcm2712/soc.yml

@@ -0,0 +1,4 @@
+series:
+- name: bcm2712
+  socs:
+  - name: bcm2712