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dts/riscv: add missing riscv,isa fields and modify existing ones

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This commit adds/modifies `riscv,isa` strings using the following rules:
* the ISA string is lowercase
* multi-letter extensions are preceded with the underscore mark
* if an extension is implied by another one, it is not specified - e.g. the
  D extension implies the F extension, so writing `rv32ifd` is redundant

Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commit is contained in:
Filip Kokosinski 2023-09-05 15:15:25 +02:00 committed by Carles Cufí
parent 9ed51516ed
commit 806c95163a
24 changed files with 41 additions and 32 deletions
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2
dts/bindings/cpu/espressif,riscv.yaml
View file

@ -5,7 +5,7 @@ description: Espressif RISC-V CPU
compatible: "espressif,riscv"
include: cpu.yaml
include: riscv,cpus.yaml
properties:
clock-source:

2
dts/bindings/cpu/intel,niosv.yaml
View file

@ -5,4 +5,4 @@ description: INTEL FPGA NIOSV Softcore Processor
compatible: "intel,niosv"
include: cpu.yaml
include: riscv,cpus.yaml

2
dts/bindings/cpu/ite,riscv-ite.yaml
View file

@ -5,4 +5,4 @@ description: ITE IT8XXX2 RISC-V CPU
compatible: "ite,riscv-ite"
include: cpu.yaml
include: riscv,cpus.yaml

2
dts/bindings/cpu/neorv32-cpu.yaml
View file

@ -5,4 +5,4 @@ description: NEORV32 RISC-V CPU
compatible: "neorv32-cpu"
include: cpu.yaml
include: riscv,cpus.yaml

2
dts/bindings/cpu/nuclei,bumblebee.yaml
View file

@ -5,7 +5,7 @@ description: Nuclei Bumblebee RISC-V Core
compatible: "nuclei,bumblebee"
include: cpu.yaml
include: riscv,cpus.yaml
properties:
mcause-exception-mask:

2
dts/bindings/cpu/telink,b91.yaml
View file

@ -5,4 +5,4 @@ description: Telink RISC-V CPU
compatible: "telink,b91"
include: cpu.yaml
include: riscv,cpus.yaml

16
dts/riscv/andes/andes_v5_ae350.dtsi
View file

@ -21,7 +21,7 @@
device_type = "cpu";
reg = <0>;
status = "okay";
riscv,isa = "rv32imafdcxandes";
riscv,isa = "rv32gc_xandes";
mmu-type = "riscv,sv32";
clock-frequency = <60000000>;
i-cache-line-size = <32>;
@ -38,7 +38,7 @@
device_type = "cpu";
reg = <1>;
status = "okay";
riscv,isa = "rv32imafdcxandes";
riscv,isa = "rv32gc_xandes";
mmu-type = "riscv,sv32";
clock-frequency = <60000000>;
i-cache-line-size = <32>;
@ -55,7 +55,7 @@
device_type = "cpu";
reg = <2>;
status = "okay";
riscv,isa = "rv32imafdcxandes";
riscv,isa = "rv32gc_xandes";
mmu-type = "riscv,sv32";
clock-frequency = <60000000>;
i-cache-line-size = <32>;
@ -72,7 +72,7 @@
device_type = "cpu";
reg = <3>;
status = "okay";
riscv,isa = "rv32imafdcxandes";
riscv,isa = "rv32gc_xandes";
mmu-type = "riscv,sv32";
clock-frequency = <60000000>;
i-cache-line-size = <32>;
@ -89,7 +89,7 @@
device_type = "cpu";
reg = <4>;
status = "okay";
riscv,isa = "rv32imafdcxandes";
riscv,isa = "rv32gc_xandes";
mmu-type = "riscv,sv32";
clock-frequency = <60000000>;
i-cache-line-size = <32>;
@ -106,7 +106,7 @@
device_type = "cpu";
reg = <5>;
status = "okay";
riscv,isa = "rv32imafdcxandes";
riscv,isa = "rv32gc_xandes";
mmu-type = "riscv,sv32";
clock-frequency = <60000000>;
i-cache-line-size = <32>;
@ -123,7 +123,7 @@
device_type = "cpu";
reg = <6>;
status = "okay";
riscv,isa = "rv32imafdcxandes";
riscv,isa = "rv32gc_xandes";
mmu-type = "riscv,sv32";
clock-frequency = <60000000>;
i-cache-line-size = <32>;
@ -140,7 +140,7 @@
device_type = "cpu";
reg = <7>;
status = "okay";
riscv,isa = "rv32imafdcxandes";
riscv,isa = "rv32gc_xandes";
mmu-type = "riscv,sv32";
clock-frequency = <60000000>;
i-cache-line-size = <32>;

2
dts/riscv/efinix/sapphire_soc.dtsi
View file

@ -30,7 +30,7 @@
compatible = "riscv";
device_type = "cpu";
reg = <0>;
riscv,isa = "rv32imac";
riscv,isa = "rv32ima_zicsr_zifencei";
status = "okay";
timebase-frequency = <100000000>;

1
dts/riscv/espressif/esp32c3/esp32c3_common.dtsi
View file

@ -32,6 +32,7 @@
cpu0: cpu@0 {
device_type = "cpu";
compatible = "espressif,riscv";
riscv,isa = "rv32imc_zicsr";
reg = <0>;
cpu-power-states = <&light_sleep &deep_sleep>;
};

1
dts/riscv/gigadevice/gd32vf103.dtsi
View file

@ -25,6 +25,7 @@
clock-frequency = <DT_FREQ_M(108)>;
mcause-exception-mask = <0x7ff>;
compatible = "nuclei,bumblebee";
riscv,isa = "rv32imac_zicsr_zifencei";
reg = <0>;
};
};

1
dts/riscv/ite/it8xxx2.dtsi
View file

@ -29,6 +29,7 @@
#size-cells = <0>;
cpu0: cpu@0 {
compatible = "ite,riscv-ite";
riscv,isa = "rv32imafc_zifencei";
device_type = "cpu";
reg = <0>;
cpu-power-states = <&standby>;

2
dts/riscv/lowrisc/opentitan_earlgrey.dtsi
View file

@ -19,7 +19,7 @@
reg = <0x00>;
status = "okay";
compatible = "riscv";
riscv,isa = "rv32imc";
riscv,isa = "rv32imcb_zicsr_zifencei";
hlic: interrupt-controller {
#interrupt-cells = <0x01>;

2
dts/riscv/microchip/microchip-miv.dtsi
View file

@ -16,7 +16,7 @@
compatible = "microchip,miv", "riscv";
device_type = "cpu";
reg = <0>;
riscv,isa = "rv32imac";
riscv,isa = "rv32ima_zicsr_zifencei";
hlic: interrupt-controller {
compatible = "riscv,cpu-intc";
#address-cells = <0>;

10
dts/riscv/microchip/mpfs-icicle.dtsi
View file

@ -19,7 +19,7 @@
compatible = "riscv";
device_type = "cpu";
reg = < 0x0 >;
riscv,isa = "rv64imac";
riscv,isa = "rv64imac_zicsr_zfencei";
hlic0: interrupt-controller {
compatible = "riscv,cpu-intc";
#address-cells = <0>;
@ -33,7 +33,7 @@
compatible = "riscv";
device_type = "cpu";
reg = < 0x1 >;
riscv,isa = "rv64imafdc";
riscv,isa = "rv64gc";
hlic1: interrupt-controller {
compatible = "riscv,cpu-intc";
#address-cells = <0>;
@ -47,7 +47,7 @@
compatible = "riscv";
device_type = "cpu";
reg = < 0x2 >;
riscv,isa = "rv64imafdc";
riscv,isa = "rv64gc";
hlic2: interrupt-controller {
compatible = "riscv,cpu-intc";
#address-cells = <0>;
@ -61,7 +61,7 @@
compatible = "riscv";
device_type = "cpu";
reg = < 0x3 >;
riscv,isa = "rv64imafdc";
riscv,isa = "rv64gc";
hlic3: interrupt-controller {
compatible = "riscv,cpu-intc";
#address-cells = <0>;
@ -75,7 +75,7 @@
compatible = "riscv";
device_type = "cpu";
reg = < 0x4 >;
riscv,isa = "rv64imafdc";
riscv,isa = "rv64gc";
hlic4: interrupt-controller {
compatible = "riscv,cpu-intc";
#address-cells = <0>;

1
dts/riscv/neorv32.dtsi
View file

@ -20,6 +20,7 @@
cpu0: cpu@0 {
compatible = "neorv32-cpu";
riscv,isa = "rv32imc_zicsr";
reg = <0>;
device_type = "cpu";

1
dts/riscv/niosv/niosv-g.dtsi
View file

@ -18,6 +18,7 @@
cpu0: cpu@0 {
device_type = "cpu";
compatible = "intel,niosv";
riscv,isa = "rv32ima_zicsr_zifencei";
reg = <0>;
clock-frequency = <50000000>;

1
dts/riscv/niosv/niosv-m.dtsi
View file

@ -18,6 +18,7 @@
cpu0: cpu@0 {
device_type = "cpu";
compatible = "intel,niosv";
riscv,isa = "rv32ia_zicsr_zifencei";
reg = <0>;
clock-frequency = <50000000>;

2
dts/riscv/openisa/rv32m1.dtsi
View file

@ -23,12 +23,14 @@
cpu@0 {
device_type = "cpu";
compatible = "riscv";
riscv,isa = "rv32ima_zicsr_zifencei";
reg = <0>;
};
cpu@1 {
device_type = "cpu";
compatible = "riscv";
riscv,isa = "rv32ima_zicsr_zifencei";
reg = <1>;
};
};

2
dts/riscv/riscv32-litex-vexriscv.dtsi
View file

@ -23,7 +23,7 @@
compatible = "riscv";
device_type = "cpu";
reg = <0>;
riscv,isa = "rv32imac";
riscv,isa = "rv32ima_zicsr_zifencei";
status = "okay";
timebase-frequency = <32768>;
};

2
dts/riscv/sifive/riscv32-fe310.dtsi
View file

@ -30,7 +30,7 @@
compatible = "sifive,e31";
device_type = "cpu";
reg = <0>;
riscv,isa = "rv32imac";
riscv,isa = "rv32imac_zicsr_zifencei";
status = "okay";
hlic: interrupt-controller {
compatible = "riscv,cpu-intc";

2
dts/riscv/sifive/riscv64-fu540.dtsi
View file

@ -36,7 +36,7 @@
compatible = "sifive,e51";
device_type = "cpu";
reg = <0>;
riscv,isa = "rv64imac";
riscv,isa = "rv64imac_zicsr_zifencei";
status = "okay";
hlic: interrupt-controller {

10
dts/riscv/sifive/riscv64-fu740.dtsi
View file

@ -35,7 +35,7 @@
compatible = "sifive,s7";
device_type = "cpu";
reg = <0>;
riscv,isa = "rv64imac";
riscv,isa = "rv64imac_zicsr_zifencei";
status = "okay";
hlic: interrupt-controller {
@ -50,7 +50,7 @@
device_type = "cpu";
mmu-type = "riscv,sv39";
reg = <0x1>;
riscv,isa = "rv64imafdc";
riscv,isa = "rv64gc";
cpu1_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
@ -63,7 +63,7 @@
device_type = "cpu";
mmu-type = "riscv,sv39";
reg = <0x2>;
riscv,isa = "rv64imafdc";
riscv,isa = "rv64gc";
cpu2_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
@ -76,7 +76,7 @@
device_type = "cpu";
mmu-type = "riscv,sv39";
reg = <0x3>;
riscv,isa = "rv64imafdc";
riscv,isa = "rv64gc";
cpu3_intc: interrupt-controller {
compatible = "riscv,cpu-intc";
@ -89,7 +89,7 @@
device_type = "cpu";
mmu-type = "riscv,sv39";
reg = <0x4>;
riscv,isa = "rv64imafdc";
riscv,isa = "rv64gc";
cpu4_intc: interrupt-controller {
compatible = "riscv,cpu-intc";

4
dts/riscv/starfive/starfive_jh7100_beagle_v.dtsi
View file

@ -35,7 +35,7 @@
mmu-type = "riscv,sv39";
next-level-cache = <&cachectrl>;
reg = <0>;
riscv,isa = "rv64imafdc";
riscv,isa = "rv64gc";
starfive,itim = <&itim0>;
status = "okay";
tlb-split;
@ -64,7 +64,7 @@
mmu-type = "riscv,sv39";
next-level-cache = <&cachectrl>;
reg = <1>;
riscv,isa = "rv64imafdc";
riscv,isa = "rv64gc";
starfive,itim = <&itim1>;
status = "okay";
tlb-split;

1
dts/riscv/telink/telink_b91.dtsi
View file

@ -23,6 +23,7 @@
reg = <0>;
clock-frequency = <24000000>;
compatible ="telink,b91", "riscv";
riscv,isa = "rv32imac_zicsr_zifencei";
};
};