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soc/it8xxx2: enable FPU support

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IT8xxx2 supports the standard 'F' extension for single-precision
floating point: select the relevant Kconfig option for the SoC so
users can build floating-point code.

Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Change-Id: Ie6da1d38d5654061553cb1ce13b0a0a96aa71ce0
This commit is contained in:
Peter Marheine 2022-04-04 11:02:57 +10:00 committed by Carles Cufí
parent 2018e5977c
commit b1ad97bc26
1 changed files with 1 additions and 0 deletions
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soc/riscv/riscv-ite/it8xxx2/Kconfig.series
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@ -5,6 +5,7 @@ config SOC_SERIES_RISCV32_IT8XXX2
bool "ITE IT8XXX2 implementation"
#depends on RISCV
select COMPRESSED_ISA
select CPU_HAS_FPU
select SOC_FAMILY_RISCV_ITE
help
Enable support for ITE IT8XXX2