snippets: Add nRF54L15 FLPR core snippets

Add snippets to boot nRF54L15 FLPR from application core.

Signed-off-by: Jakub Zymelka <jakub.zymelka@nordicsemi.no>
This commit is contained in:
Jakub Zymelka 2024-03-28 17:38:16 +01:00 committed by Fabio Baltieri
parent 65f743619d
commit bec4faebb9
8 changed files with 128 additions and 0 deletions

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.. _nordic-flpr-xip:
Nordic FLPR snippet with execution in place (nordic-flpr-xip)
#############################################################
Overview
********
This snippet allows users to build Zephyr with the capability to boot Nordic FLPR
(Fast Lightweight Peripheral Processor) from application core.
FLPR code is to be executed from RRAM, so the FLPR image must be built
for the ``xip`` board variant, or with :kconfig:option:`CONFIG_XIP` enabled.

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/*
* Copyright (c) 2024 Nordic Semiconductor
* SPDX-License-Identifier: Apache-2.0
*/
/ {
soc {
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
cpuflpr_code_partition: image@165000 {
/* FLPR core code partition */
reg = <0x165000 DT_SIZE_K(96)>;
};
};
};
};
&uart30 {
status = "reserved";
};
&cpuflpr_vpr {
execution-memory = <&cpuflpr_code_partition>;
};

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/*
* Copyright (c) 2024 Nordic Semiconductor
* SPDX-License-Identifier: Apache-2.0
*/
&cpuflpr_vpr {
status = "okay";
};
&cpuflpr_vevif_remote {
status = "okay";
};

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name: nordic-flpr-xip
append:
EXTRA_DTC_OVERLAY_FILE: nordic-flpr-xip.overlay
boards:
nrf54l15pdk/nrf54l15/cpuapp:
append:
EXTRA_DTC_OVERLAY_FILE: boards/nrf54l15pdk_nrf54l15_cpuapp.overlay

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.. _nordic-flpr:
Nordic FLPR snippet with execution from SRAM (nordic-flpr)
##########################################################
Overview
********
This snippet allows users to build Zephyr with the capability to boot Nordic FLPR
(Fast Lightweight Peripheral Processor) from application core.
FLPR code is to be executed from SRAM, so the FLPR image must be built
without the ``xip`` board variant, or with :kconfig:option:`CONFIG_XIP` disabled.

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/*
* Copyright (c) 2024 Nordic Semiconductor
* SPDX-License-Identifier: Apache-2.0
*/
/ {
soc {
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
cpuflpr_code_partition: image@165000 {
/* FLPR core code partition */
reg = <0x165000 DT_SIZE_K(96)>;
};
};
cpuflpr_sram_code_data: memory@20028000 {
compatible = "mmio-sram";
reg = <0x20028000 DT_SIZE_K(96)>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x20028000 0x18000>;
};
};
};
&uart30 {
status = "reserved";
};
&cpuapp_sram {
reg = <0x20000000 DT_SIZE_K(160)>;
ranges = <0x0 0x20000000 0x28000>;
};
&cpuflpr_vpr {
execution-memory = <&cpuflpr_sram_code_data>;
source-memory = <&cpuflpr_code_partition>;
};

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/*
* Copyright (c) 2024 Nordic Semiconductor
* SPDX-License-Identifier: Apache-2.0
*/
&cpuflpr_vpr {
status = "okay";
};
&cpuflpr_vevif_remote {
status = "okay";
};

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name: nordic-flpr
append:
EXTRA_DTC_OVERLAY_FILE: nordic-flpr.overlay
boards:
nrf54l15pdk/nrf54l15/cpuapp:
append:
EXTRA_DTC_OVERLAY_FILE: boards/nrf54l15pdk_nrf54l15_cpuapp.overlay