drivers: pinctrl: Add LPC IOCON pinctrl driver

Add lpc iocon pinctrl driver. Driver handles IOCON clock initialization as
well as IOCON pin configuration

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This commit is contained in:
Daniel DeGrasse 2022-03-04 14:31:23 -06:00 committed by Marti Bolivar
parent 9226cf338e
commit c133e357ef
4 changed files with 70 additions and 0 deletions

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@ -16,3 +16,4 @@ zephyr_library_sources_ifdef(CONFIG_PINCTRL_NXP_KINETIS pinctrl_kinetis.c)
zephyr_library_sources_ifdef(CONFIG_PINCTRL_MCHP_XEC pinctrl_mchp_xec.c)
zephyr_library_sources_ifdef(CONFIG_PINCTRL_MCUX_RT pinctrl_mcux_rt.c)
zephyr_library_sources_ifdef(CONFIG_PINCTRL_SIFIVE pinctrl_sifive.c)
zephyr_library_sources_ifdef(CONFIG_PINCTRL_NXP_IOCON pinctrl_lpc_iocon.c)

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@ -41,5 +41,6 @@ source "drivers/pinctrl/Kconfig.kinetis"
source "drivers/pinctrl/Kconfig.xec"
source "drivers/pinctrl/Kconfig.mcux"
source "drivers/pinctrl/Kconfig.sifive"
source "drivers/pinctrl/Kconfig.lpc_iocon"
endif # PINCTRL

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@ -0,0 +1,11 @@
# Copyright (c) 2022 NXP
# SPDX-License-Identifier: Apache-2.0
DT_COMPAT_NXP_LPC_PINCTRL := nxp,lpc-iocon-pinctrl
config PINCTRL_NXP_IOCON
bool "IOCON Pin controller driver for NXP LPC MCUs"
depends on SOC_FAMILY_LPC
default $(dt_compat_enabled,$(DT_COMPAT_NXP_LPC_PINCTRL))
help
Enable pin controller driver for NXP LPC MCUs

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@ -0,0 +1,57 @@
/*
* Copyright (c) 2022, NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <drivers/pinctrl.h>
#include <fsl_clock.h>
#define PORT(mux) (((mux) & 0xC0000000) >> 30)
#define PIN(mux) (((mux) & 0x3F000000) >> 24)
#define TYPE(mux) (((mux) & 0xC00000) >> 22)
#define IOCON_TYPE_D 0x0
#define IOCON_TYPE_I 0x1
#define IOCON_TYPE_A 0x2
static IOCON_Type *iocon = (IOCON_Type *)DT_REG_ADDR(DT_NODELABEL(iocon));
int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
uintptr_t reg)
{
for (uint8_t i = 0; i < pin_cnt; i++) {
/* Check if this is an analog or i2c type pin */
uint32_t pin_mux = pins[i];
uint32_t port = PORT(pin_mux);
uint32_t pin = PIN(pin_mux);
switch (TYPE(pin_mux)) {
case IOCON_TYPE_D:
pin_mux &= Z_PINCTRL_IOCON_D_PIN_MASK;
break;
case IOCON_TYPE_I:
pin_mux &= Z_PINCTRL_IOCON_I_PIN_MASK;
break;
case IOCON_TYPE_A:
pin_mux &= Z_PINCTRL_IOCON_A_PIN_MASK;
break;
default:
/* Should not occur */
assert(TYPE(pin_mux <= IOCON_TYPE_A));
}
/* Set pinmux */
iocon->PIO[port][pin] = pin_mux;
}
return 0;
}
static int pinctrl_clock_init(const struct device *dev)
{
ARG_UNUSED(dev);
/* Enable IOCon clock */
CLOCK_EnableClock(kCLOCK_Iocon);
return 0;
}
SYS_INIT(pinctrl_clock_init, PRE_KERNEL_1, 0);