drivers: all: imx: remove conditional support for pinctrl
The iMX platform always uses pinctrl, there's no need to keep extra macrology around pinctrl. Also updated driver's Kconfig to `select PINCTRL`. Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
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b2d9212ea0
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c4c5f57d59
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@ -8,5 +8,6 @@ config GPIO_IMX
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default y
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depends on HAS_IMX_GPIO
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depends on DT_HAS_NXP_IMX_GPIO_ENABLED
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select PINCTRL
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help
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Enable the IMX GPIO driver.
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@ -14,9 +14,7 @@
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#include <zephyr/sys/util.h>
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#include <gpio_imx.h>
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#include <string.h>
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#ifdef CONFIG_PINCTRL
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#include <zephyr/drivers/pinctrl.h>
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#endif
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#include <zephyr/drivers/gpio/gpio_utils.h>
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@ -24,10 +22,8 @@ struct imx_gpio_config {
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/* gpio_driver_config needs to be first */
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struct gpio_driver_config common;
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GPIO_Type *base;
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#ifdef CONFIG_PINCTRL
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const struct pinctrl_soc_pinmux *pin_muxes;
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uint8_t mux_count;
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#endif
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};
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struct imx_gpio_data {
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@ -46,7 +42,6 @@ static int imx_gpio_configure(const struct device *port, gpio_pin_t pin,
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if (((flags & GPIO_INPUT) != 0U) && ((flags & GPIO_OUTPUT) != 0U)) {
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return -ENOTSUP;
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}
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#ifdef CONFIG_PINCTRL
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__ASSERT_NO_MSG(pin < config->mux_count);
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struct pinctrl_soc_pin pin_cfg;
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@ -92,14 +87,6 @@ static int imx_gpio_configure(const struct device *port, gpio_pin_t pin,
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pin_cfg.pin_ctrl_flags = reg;
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pinctrl_configure_pins(&pin_cfg, 1, PINCTRL_REG_NONE);
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#else /*CONFIG_PINCTRL */
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if ((flags & (GPIO_SINGLE_ENDED
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| GPIO_PULL_UP
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| GPIO_PULL_DOWN)) != 0U) {
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return -ENOTSUP;
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}
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#endif
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/* Disable interrupts for pin */
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GPIO_SetPinIntMode(base, pin, false);
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GPIO_SetIntEdgeSelect(base, pin, false);
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@ -263,7 +250,6 @@ static const struct gpio_driver_api imx_gpio_driver_api = {
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.manage_callback = imx_gpio_manage_callback,
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};
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#ifdef CONFIG_PINCTRL
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/* These macros will declare an array of pinctrl_soc_pinmux types */
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#define PINMUX_INIT(node, prop, idx) MCUX_IMX_PINMUX(DT_PROP_BY_IDX(node, prop, idx)),
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#define IMX_IGPIO_PIN_DECLARE(n) \
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@ -273,10 +259,6 @@ static const struct gpio_driver_api imx_gpio_driver_api = {
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#define IMX_IGPIO_PIN_INIT(n) \
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.pin_muxes = mcux_igpio_pinmux_##n, \
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.mux_count = DT_INST_PROP_LEN(n, pinmux),
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#else
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#define IMX_IGPIO_PIN_DECLARE(n)
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#define IMX_IGPIO_PIN_INIT(n)
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#endif /* CONFIG_PINCTRL */
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#define GPIO_IMX_INIT(n) \
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IMX_IGPIO_PIN_DECLARE(n) \
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@ -7,6 +7,7 @@ config IMX_USDHC
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depends on DT_HAS_NXP_IMX_USDHC_ENABLED
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select SDHC_SUPPORTS_UHS
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select SDHC_SUPPORTS_NATIVE_MODE
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select PINCTRL
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help
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Enable the NXP IMX SD Host controller driver
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@ -15,13 +15,11 @@
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#include <zephyr/drivers/gpio.h>
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#include <zephyr/logging/log.h>
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#include <soc.h>
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#ifdef CONFIG_PINCTRL
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#include <zephyr/drivers/pinctrl.h>
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#define PINCTRL_STATE_SLOW PINCTRL_STATE_PRIV_START
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#define PINCTRL_STATE_MED (PINCTRL_STATE_PRIV_START + 1U)
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#define PINCTRL_STATE_FAST (PINCTRL_STATE_PRIV_START + 2U)
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#define PINCTRL_STATE_NOPULL (PINCTRL_STATE_PRIV_START + 3U)
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#endif
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LOG_MODULE_REGISTER(usdhc, CONFIG_SDHC_LOG_LEVEL);
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@ -72,9 +70,7 @@ struct usdhc_config {
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uint32_t max_bus_freq;
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bool mmc_hs200_1_8v;
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bool mmc_hs400_1_8v;
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#ifdef CONFIG_PINCTRL
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const struct pinctrl_dev_config *pincfg;
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#endif
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void (*irq_config_func)(const struct device *dev);
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};
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@ -115,16 +111,11 @@ static int imx_usdhc_dat3_pull(const struct usdhc_config *cfg, bool pullup)
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{
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int ret = 0U;
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#ifdef CONFIG_PINCTRL
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ret = pinctrl_apply_state(cfg->pincfg, PINCTRL_STATE_NOPULL);
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if (ret) {
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LOG_ERR("No DAT3 floating state defined, but dat3 detect selected");
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return ret;
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}
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#else
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/* Call board specific function to pull down DAT3 */
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imxrt_usdhc_dat3_pull(pullup);
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#endif
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#ifdef CONFIG_IMX_USDHC_DAT3_PWR_TOGGLE
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if (!pullup) {
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/* Power off the card to clear DAT3 legacy status */
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@ -364,18 +355,10 @@ static int imx_usdhc_set_io(const struct device *dev, struct sdhc_io *ios)
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break;
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case SDHC_TIMING_SDR12:
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case SDHC_TIMING_SDR25:
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#ifdef CONFIG_PINCTRL
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pinctrl_apply_state(cfg->pincfg, PINCTRL_STATE_SLOW);
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#else
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imxrt_usdhc_pinmux(cfg->nusdhc, false, 0, 7);
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#endif
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break;
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case SDHC_TIMING_SDR50:
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#ifdef CONFIG_PINCTRL
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pinctrl_apply_state(cfg->pincfg, PINCTRL_STATE_MED);
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#else
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imxrt_usdhc_pinmux(cfg->nusdhc, false, 2, 7);
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#endif
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break;
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case SDHC_TIMING_HS400:
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#if FSL_FEATURE_USDHC_HAS_HS400_MODE
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@ -391,11 +374,7 @@ static int imx_usdhc_set_io(const struct device *dev, struct sdhc_io *ios)
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case SDHC_TIMING_DDR50:
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case SDHC_TIMING_DDR52:
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case SDHC_TIMING_HS200:
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#ifdef CONFIG_PINCTRL
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pinctrl_apply_state(cfg->pincfg, PINCTRL_STATE_FAST);
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#else
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imxrt_usdhc_pinmux(cfg->nusdhc, false, 3, 7);
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#endif
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break;
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default:
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return -ENOTSUP;
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@ -823,12 +802,10 @@ static int imx_usdhc_init(const struct device *dev)
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return -ENODEV;
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}
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#ifdef CONFIG_PINCTRL
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ret = pinctrl_apply_state(cfg->pincfg, PINCTRL_STATE_DEFAULT);
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if (ret) {
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return ret;
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}
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#endif
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USDHC_TransferCreateHandle(cfg->base, &data->transfer_handle,
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&callbacks, (void *)dev);
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cfg->irq_config_func(dev);
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@ -872,14 +849,6 @@ static const struct sdhc_driver_api usdhc_api = {
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.get_host_props = imx_usdhc_get_host_props,
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};
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#ifdef CONFIG_PINCTRL
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#define IMX_USDHC_PINCTRL_DEFINE(n) PINCTRL_DT_INST_DEFINE(n);
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#define IMX_USDHC_PINCTRL_INIT(n) .pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n),
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#else
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#define IMX_USDHC_PINCTRL_DEFINE(n)
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#define IMX_USDHC_PINCTRL_INIT(n)
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#endif
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#ifdef CONFIG_NOCACHE_MEMORY
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#define IMX_USDHC_NOCACHE_TAG __attribute__((__section__(".nocache")));
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#else
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@ -909,7 +878,7 @@ static const struct sdhc_driver_api usdhc_api = {
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irq_enable(DT_INST_IRQN(n)); \
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} \
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\
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IMX_USDHC_PINCTRL_DEFINE(n) \
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PINCTRL_DT_INST_DEFINE(n); \
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\
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static const struct usdhc_config usdhc_##n##_config = { \
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.base = (USDHC_Type *) DT_INST_REG_ADDR(n), \
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@ -932,7 +901,7 @@ static const struct sdhc_driver_api usdhc_api = {
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.mmc_hs200_1_8v = DT_INST_PROP(n, mmc_hs200_1_8v), \
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.mmc_hs400_1_8v = DT_INST_PROP(n, mmc_hs400_1_8v), \
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.irq_config_func = usdhc_##n##_irq_config_func, \
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IMX_USDHC_PINCTRL_INIT(n) \
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.pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
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}; \
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\
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\
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