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gpio: remove port access op support

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The only remaining port operations have dedicated API function table
entries.  Remove the defines for access op (mode), and remove support
for access op from all implementations.

Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
This commit is contained in:
Peter Bigot 2020-01-30 09:31:07 -06:00 committed by Carles Cufí
parent 1f9beb193f
commit c7d526be04
27 changed files with 92 additions and 280 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

6
drivers/gpio/gpio_cc13xx_cc26xx.c
View file

@ -41,15 +41,11 @@ static int gpio_cc13xx_cc26xx_port_set_bits_raw(struct device *port,
static int gpio_cc13xx_cc26xx_port_clear_bits_raw(struct device *port, static int gpio_cc13xx_cc26xx_port_clear_bits_raw(struct device *port,
u32_t mask); u32_t mask);
static int gpio_cc13xx_cc26xx_config(struct device *port, int access_op, static int gpio_cc13xx_cc26xx_config(struct device *port,
u32_t pin, int flags) u32_t pin, int flags)
{ {
u32_t config = 0; u32_t config = 0;
if (access_op != GPIO_ACCESS_BY_PIN) {
return -ENOTSUP;
}
__ASSERT_NO_MSG(pin < NUM_IO_MAX); __ASSERT_NO_MSG(pin < NUM_IO_MAX);
switch (flags & (GPIO_INPUT | GPIO_OUTPUT)) { switch (flags & (GPIO_INPUT | GPIO_OUTPUT)) {

6
drivers/gpio/gpio_cc32xx.c
View file

@ -70,7 +70,7 @@ static int gpio_cc32xx_port_set_bits_raw(struct device *port, u32_t mask);
static int gpio_cc32xx_port_clear_bits_raw(struct device *port, u32_t mask); static int gpio_cc32xx_port_clear_bits_raw(struct device *port, u32_t mask);
static inline int gpio_cc32xx_config(struct device *port, static inline int gpio_cc32xx_config(struct device *port,
int access_op, u32_t pin, int flags) u32_t pin, int flags)
{ {
const struct gpio_cc32xx_config *gpio_config = DEV_CFG(port); const struct gpio_cc32xx_config *gpio_config = DEV_CFG(port);
unsigned long port_base = gpio_config->port_base; unsigned long port_base = gpio_config->port_base;
@ -87,10 +87,6 @@ static inline int gpio_cc32xx_config(struct device *port,
return -ENOTSUP; return -ENOTSUP;
} }
if (access_op != GPIO_ACCESS_BY_PIN) {
return -ENOTSUP;
}
MAP_PinTypeGPIO(pinTable[gpio_config->port_num * 8 + pin], MAP_PinTypeGPIO(pinTable[gpio_config->port_num * 8 + pin],
PIN_MODE_0, false); PIN_MODE_0, false);
if (flags & GPIO_OUTPUT) { if (flags & GPIO_OUTPUT) {

18
drivers/gpio/gpio_cmsdk_ahb.c
View file

@ -130,29 +130,15 @@ static int cmsdk_ahb_gpio_config(struct device *dev, u32_t mask, int flags)
* @brief Configure pin or port * @brief Configure pin or port
* *
* @param dev Device struct * @param dev Device struct
* @param access_op Access operation (pin or port)
* @param pin The pin number * @param pin The pin number
* @param flags Flags of pin or port * @param flags Flags of pin or port
* *
* @return 0 if successful, failed otherwise * @return 0 if successful, failed otherwise
*/ */
static int gpio_cmsdk_ahb_config(struct device *dev, int access_op, static int gpio_cmsdk_ahb_config(struct device *dev,
u32_t pin, int flags) u32_t pin, int flags)
{ {
int ret = 0; return cmsdk_ahb_gpio_config(dev, BIT(pin), flags);
switch (access_op) {
case GPIO_ACCESS_BY_PIN:
ret = cmsdk_ahb_gpio_config(dev, BIT(pin), flags);
break;
case GPIO_ACCESS_BY_PORT:
ret = cmsdk_ahb_gpio_config(dev, (0xFFFF), flags);
break;
default:
return -ENOTSUP;
}
return ret;
} }
static int gpio_cmsdk_ahb_pin_interrupt_configure(struct device *dev, static int gpio_cmsdk_ahb_pin_interrupt_configure(struct device *dev,

18
drivers/gpio/gpio_dw.c
View file

@ -301,17 +301,7 @@ static inline void dw_pin_config(struct device *port,
} }
} }
static inline void dw_port_config(struct device *port, int flags) static inline int gpio_dw_config(struct device *port,
{
const struct gpio_dw_config *config = port->config->config_info;
int i;
for (i = 0; i < config->bits; i++) {
dw_pin_config(port, i, flags);
}
}
static inline int gpio_dw_config(struct device *port, int access_op,
u32_t pin, int flags) u32_t pin, int flags)
{ {
const struct gpio_dw_config *config = port->config->config_info; const struct gpio_dw_config *config = port->config->config_info;
@ -341,11 +331,7 @@ static inline int gpio_dw_config(struct device *port, int access_op,
return -ENOTSUP; return -ENOTSUP;
} }
if (GPIO_ACCESS_BY_PIN == access_op) { dw_pin_config(port, pin, flags);
dw_pin_config(port, pin, flags);
} else {
dw_port_config(port, flags);
}
return 0; return 0;
} }

6
drivers/gpio/gpio_esp32.c
View file

@ -55,7 +55,7 @@ struct gpio_esp32_data {
sys_slist_t cb; sys_slist_t cb;
}; };
static int gpio_esp32_config(struct device *dev, int access_op, static int gpio_esp32_config(struct device *dev,
u32_t pin, int flags) u32_t pin, int flags)
{ {
struct gpio_esp32_data *data = dev->driver_data; struct gpio_esp32_data *data = dev->driver_data;
@ -64,10 +64,6 @@ static int gpio_esp32_config(struct device *dev, int access_op,
u32_t func; u32_t func;
int r; int r;
if (access_op != GPIO_ACCESS_BY_PIN) {
return -ENOTSUP;
}
/* Query pinmux to validate pin number. */ /* Query pinmux to validate pin number. */
r = pinmux_pin_get(data->pinmux, io_pin, &func); r = pinmux_pin_get(data->pinmux, io_pin, &func);
if (r < 0) { if (r < 0) {

27
drivers/gpio/gpio_gecko.c
View file

@ -71,19 +71,13 @@ static inline void gpio_gecko_add_port(struct gpio_gecko_common_data *data,
} }
static int gpio_gecko_configure(struct device *dev, static int gpio_gecko_configure(struct device *dev,
int access_op, u32_t pin, int flags) u32_t pin, int flags)
{ {
const struct gpio_gecko_config *config = dev->config->config_info; const struct gpio_gecko_config *config = dev->config->config_info;
GPIO_P_TypeDef *gpio_base = config->gpio_base;
GPIO_Port_TypeDef gpio_index = config->gpio_index; GPIO_Port_TypeDef gpio_index = config->gpio_index;
GPIO_Mode_TypeDef mode; GPIO_Mode_TypeDef mode;
unsigned int out = 0U; unsigned int out = 0U;
/* Setting interrupt flags for a complete port is not implemented */
if ((flags & GPIO_INT_ENABLE) && (access_op == GPIO_ACCESS_BY_PORT)) {
return -ENOTSUP;
}
if (flags & GPIO_OUTPUT) { if (flags & GPIO_OUTPUT) {
/* Following modes enable both output and input */ /* Following modes enable both output and input */
if (flags & GPIO_SINGLE_ENDED) { if (flags & GPIO_SINGLE_ENDED) {
@ -123,24 +117,7 @@ static int gpio_gecko_configure(struct device *dev,
* 0 - pin is input, 1 - pin is output * 0 - pin is input, 1 - pin is output
*/ */
if (access_op == GPIO_ACCESS_BY_PIN) { GPIO_PinModeSet(gpio_index, pin, mode, out);
GPIO_PinModeSet(gpio_index, pin, mode, out);
} else { /* GPIO_ACCESS_BY_PORT */
gpio_base->MODEL = GECKO_GPIO_MODEL(7, mode)
| GECKO_GPIO_MODEL(6, mode) | GECKO_GPIO_MODEL(5, mode)
| GECKO_GPIO_MODEL(4, mode) | GECKO_GPIO_MODEL(3, mode)
| GECKO_GPIO_MODEL(2, mode) | GECKO_GPIO_MODEL(1, mode)
| GECKO_GPIO_MODEL(0, mode);
gpio_base->MODEH = GECKO_GPIO_MODEH(15, mode)
| GECKO_GPIO_MODEH(14, mode)
| GECKO_GPIO_MODEH(13, mode)
| GECKO_GPIO_MODEH(12, mode)
| GECKO_GPIO_MODEH(11, mode)
| GECKO_GPIO_MODEH(10, mode)
| GECKO_GPIO_MODEH(9, mode)
| GECKO_GPIO_MODEH(8, mode);
gpio_base->DOUT = (out ? 0xFFFF : 0x0000);
}
return 0; return 0;
} }

4
drivers/gpio/gpio_handlers.c
View file

@ -7,11 +7,11 @@
#include <drivers/gpio.h> #include <drivers/gpio.h>
#include <syscall_handler.h> #include <syscall_handler.h>
static inline int z_vrfy_gpio_config(struct device *port, int access_op, static inline int z_vrfy_gpio_config(struct device *port,
u32_t pin, gpio_flags_t flags) u32_t pin, gpio_flags_t flags)
{ {
Z_OOPS(Z_SYSCALL_DRIVER_GPIO(port, config)); Z_OOPS(Z_SYSCALL_DRIVER_GPIO(port, config));
return z_impl_gpio_config((struct device *)port, access_op, pin, flags); return z_impl_gpio_config((struct device *)port, pin, flags);
} }
#include <syscalls/gpio_config_mrsh.c> #include <syscalls/gpio_config_mrsh.c>

3
drivers/gpio/gpio_ht16k33.c
View file

@ -37,11 +37,10 @@ struct gpio_ht16k33_data {
sys_slist_t callbacks; sys_slist_t callbacks;
}; };
static int gpio_ht16k33_cfg(struct device *dev, int access_op, static int gpio_ht16k33_cfg(struct device *dev,
u32_t pin, int flags) u32_t pin, int flags)
{ {
ARG_UNUSED(dev); ARG_UNUSED(dev);
ARG_UNUSED(access_op);
ARG_UNUSED(pin); ARG_UNUSED(pin);
/* Keyscan is input-only */ /* Keyscan is input-only */

6
drivers/gpio/gpio_imx.c
View file

@ -28,16 +28,12 @@ struct imx_gpio_data {
u32_t pin_callback_enables; u32_t pin_callback_enables;
}; };
static int imx_gpio_configure(struct device *port, int access_op, u32_t pin, static int imx_gpio_configure(struct device *port, u32_t pin,
int flags) int flags)
{ {
const struct imx_gpio_config *config = port->config->config_info; const struct imx_gpio_config *config = port->config->config_info;
GPIO_Type *base = config->base; GPIO_Type *base = config->base;
if (access_op != GPIO_ACCESS_BY_PIN) {
return -ENOTSUP;
}
if (((flags & GPIO_INPUT) != 0U) && ((flags & GPIO_OUTPUT) != 0U)) { if (((flags & GPIO_INPUT) != 0U) && ((flags & GPIO_OUTPUT) != 0U)) {
return -ENOTSUP; return -ENOTSUP;
} }

6
drivers/gpio/gpio_intel_apl.c
View file

@ -205,17 +205,13 @@ static int gpio_intel_apl_isr(struct device *dev)
return 0; return 0;
} }
static int gpio_intel_apl_config(struct device *dev, int access_op, static int gpio_intel_apl_config(struct device *dev,
u32_t pin, int flags) u32_t pin, int flags)
{ {
const struct gpio_intel_apl_config *cfg = dev->config->config_info; const struct gpio_intel_apl_config *cfg = dev->config->config_info;
struct gpio_intel_apl_data *data = dev->driver_data; struct gpio_intel_apl_data *data = dev->driver_data;
u32_t raw_pin, reg, cfg0, cfg1; u32_t raw_pin, reg, cfg0, cfg1;
if (access_op != GPIO_ACCESS_BY_PIN) {
return -ENOTSUP;
}
/* Only support push-pull mode */ /* Only support push-pull mode */
if ((flags & GPIO_SINGLE_ENDED) != 0U) { if ((flags & GPIO_SINGLE_ENDED) != 0U) {
return -ENOTSUP; return -ENOTSUP;

6
drivers/gpio/gpio_litex.c
View file

@ -89,15 +89,11 @@ static int gpio_litex_init(struct device *dev)
return 0; return 0;
} }
static int gpio_litex_configure(struct device *dev, int access_op, static int gpio_litex_configure(struct device *dev,
u32_t pin, int flags) u32_t pin, int flags)
{ {
const struct gpio_litex_cfg *gpio_config = DEV_GPIO_CFG(dev); const struct gpio_litex_cfg *gpio_config = DEV_GPIO_CFG(dev);
if (access_op != GPIO_ACCESS_BY_PIN) {
return -ENOTSUP;
}
if (flags & ~SUPPORTED_FLAGS) { if (flags & ~SUPPORTED_FLAGS) {
return -ENOTSUP; return -ENOTSUP;
} }

6
drivers/gpio/gpio_lmp90xxx.c
View file

@ -32,16 +32,12 @@ struct gpio_lmp90xxx_data {
struct device *parent; struct device *parent;
}; };
static int gpio_lmp90xxx_config(struct device *dev, int access_op, static int gpio_lmp90xxx_config(struct device *dev,
u32_t pin, int flags) u32_t pin, int flags)
{ {
struct gpio_lmp90xxx_data *data = dev->driver_data; struct gpio_lmp90xxx_data *data = dev->driver_data;
int err = 0; int err = 0;
if (access_op != GPIO_ACCESS_BY_PIN) {
return -ENOTSUP;
}
if (pin > LMP90XXX_GPIO_MAX) { if (pin > LMP90XXX_GPIO_MAX) {
return -EINVAL; return -EINVAL;
} }

24
drivers/gpio/gpio_mchp_xec.c
View file

@ -45,7 +45,7 @@ struct gpio_xec_config {
}; };
static int gpio_xec_configure(struct device *dev, static int gpio_xec_configure(struct device *dev,
int access_op, u32_t pin, int flags) u32_t pin, int flags)
{ {
const struct gpio_xec_config *config = dev->config->config_info; const struct gpio_xec_config *config = dev->config->config_info;
__IO u32_t *current_pcr1; __IO u32_t *current_pcr1;
@ -72,20 +72,16 @@ static int gpio_xec_configure(struct device *dev,
*/ */
mask |= MCHP_GPIO_CTRL_DIR_MASK; mask |= MCHP_GPIO_CTRL_DIR_MASK;
mask |= MCHP_GPIO_CTRL_INPAD_DIS_MASK; mask |= MCHP_GPIO_CTRL_INPAD_DIS_MASK;
if (access_op == GPIO_ACCESS_BY_PIN) { if ((flags & GPIO_OUTPUT) != 0U) {
if ((flags & GPIO_OUTPUT) != 0U) { if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0U) {
if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0U) { *gpio_out_reg |= BIT(pin);
*gpio_out_reg |= BIT(pin); } else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0U) {
} else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0U) { *gpio_out_reg &= ~BIT(pin);
*gpio_out_reg &= ~BIT(pin);
}
pcr1 |= MCHP_GPIO_CTRL_DIR_OUTPUT;
} else {
/* GPIO_INPUT */
pcr1 |= MCHP_GPIO_CTRL_DIR_INPUT;
} }
} else { /* GPIO_ACCESS_BY_PORT is not supported */ pcr1 |= MCHP_GPIO_CTRL_DIR_OUTPUT;
return -ENOTSUP; } else {
/* GPIO_INPUT */
pcr1 |= MCHP_GPIO_CTRL_DIR_INPUT;
} }
/* Figure out the pullup/pulldown configuration and keep it in the /* Figure out the pullup/pulldown configuration and keep it in the

50
drivers/gpio/gpio_mcux.c
View file

@ -32,14 +32,13 @@ struct gpio_mcux_data {
}; };
static int gpio_mcux_configure(struct device *dev, static int gpio_mcux_configure(struct device *dev,
int access_op, u32_t pin, int flags) u32_t pin, int flags)
{ {
const struct gpio_mcux_config *config = dev->config->config_info; const struct gpio_mcux_config *config = dev->config->config_info;
GPIO_Type *gpio_base = config->gpio_base; GPIO_Type *gpio_base = config->gpio_base;
PORT_Type *port_base = config->port_base; PORT_Type *port_base = config->port_base;
u32_t mask = 0U; u32_t mask = 0U;
u32_t pcr = 0U; u32_t pcr = 0U;
u8_t i;
/* Check for an invalid pin number */ /* Check for an invalid pin number */
if (pin >= ARRAY_SIZE(port_base->PCR)) { if (pin >= ARRAY_SIZE(port_base->PCR)) {
@ -61,28 +60,20 @@ static int gpio_mcux_configure(struct device *dev,
* 0 - pin is input, 1 - pin is output * 0 - pin is input, 1 - pin is output
*/ */
if (access_op == GPIO_ACCESS_BY_PIN) { switch (flags & GPIO_DIR_MASK) {
switch (flags & GPIO_DIR_MASK) { case GPIO_INPUT:
case GPIO_INPUT: gpio_base->PDDR &= ~BIT(pin);
gpio_base->PDDR &= ~BIT(pin); break;
break; case GPIO_OUTPUT:
case GPIO_OUTPUT: if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) {
if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) { gpio_base->PSOR = BIT(pin);
gpio_base->PSOR = BIT(pin); } else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0) {
} else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0) { gpio_base->PCOR = BIT(pin);
gpio_base->PCOR = BIT(pin);
}
gpio_base->PDDR |= BIT(pin);
break;
default:
return -ENOTSUP;
}
} else { /* GPIO_ACCESS_BY_PORT */
if ((flags & GPIO_INPUT) != 0) {
gpio_base->PDDR = 0x0;
} else { /* GPIO_OUTPUT */
gpio_base->PDDR = 0xFFFFFFFF;
} }
gpio_base->PDDR |= BIT(pin);
break;
default:
return -ENOTSUP;
} }
/* Now do the PORT module. Figure out the pullup/pulldown /* Now do the PORT module. Figure out the pullup/pulldown
@ -101,17 +92,8 @@ static int gpio_mcux_configure(struct device *dev,
pcr |= PORT_PCR_PE_MASK; pcr |= PORT_PCR_PE_MASK;
} }
/* Now we can write the PORT PCR register(s). If accessing by pin, we /* Accessing by pin, we only need to write one PCR register. */
* only need to write one PCR register. Otherwise, write all the PCR port_base->PCR[pin] = (port_base->PCR[pin] & ~mask) | pcr;
* registers in the PORT module (one for each pin).
*/
if (access_op == GPIO_ACCESS_BY_PIN) {
port_base->PCR[pin] = (port_base->PCR[pin] & ~mask) | pcr;
} else { /* GPIO_ACCESS_BY_PORT */
for (i = 0U; i < ARRAY_SIZE(port_base->PCR); i++) {
port_base->PCR[i] = (port_base->PCR[pin] & ~mask) | pcr;
}
}
return 0; return 0;
} }

6
drivers/gpio/gpio_mcux_igpio.c
View file

@ -29,7 +29,7 @@ struct mcux_igpio_data {
}; };
static int mcux_igpio_configure(struct device *dev, static int mcux_igpio_configure(struct device *dev,
int access_op, u32_t pin, int flags) u32_t pin, int flags)
{ {
const struct mcux_igpio_config *config = dev->config->config_info; const struct mcux_igpio_config *config = dev->config->config_info;
GPIO_Type *base = config->base; GPIO_Type *base = config->base;
@ -46,10 +46,6 @@ static int mcux_igpio_configure(struct device *dev,
return -ENOTSUP; return -ENOTSUP;
} }
if (access_op == GPIO_ACCESS_BY_PORT) {
return -ENOTSUP;
}
if (flags & GPIO_OUTPUT_INIT_HIGH) { if (flags & GPIO_OUTPUT_INIT_HIGH) {
base->DR_SET = BIT(pin); base->DR_SET = BIT(pin);
} }

24
drivers/gpio/gpio_mcux_lpc.c
View file

@ -56,7 +56,7 @@ struct gpio_mcux_lpc_data {
u32_t isr_list_idx; u32_t isr_list_idx;
}; };
static int gpio_mcux_lpc_configure(struct device *dev, int access_op, u32_t pin, static int gpio_mcux_lpc_configure(struct device *dev, u32_t pin,
int flags) int flags)
{ {
const struct gpio_mcux_lpc_config *config = dev->config->config_info; const struct gpio_mcux_lpc_config *config = dev->config->config_info;
@ -84,21 +84,17 @@ static int gpio_mcux_lpc_configure(struct device *dev, int access_op, u32_t pin,
} }
/* supports access by pin now,you can add access by port when needed */ /* supports access by pin now,you can add access by port when needed */
if (access_op == GPIO_ACCESS_BY_PIN) { if (flags & GPIO_OUTPUT_INIT_HIGH) {
if (flags & GPIO_OUTPUT_INIT_HIGH) { gpio_base->SET[port] = BIT(pin);
gpio_base->SET[port] = BIT(pin);
}
if (flags & GPIO_OUTPUT_INIT_LOW) {
gpio_base->CLR[port] = BIT(pin);
}
/* input-0,output-1 */
WRITE_BIT(gpio_base->DIR[port], pin, flags & GPIO_OUTPUT);
} else {
return -EINVAL;
} }
if (flags & GPIO_OUTPUT_INIT_LOW) {
gpio_base->CLR[port] = BIT(pin);
}
/* input-0,output-1 */
WRITE_BIT(gpio_base->DIR[port], pin, flags & GPIO_OUTPUT);
return 0; return 0;
} }

2
drivers/gpio/gpio_mmio32.c
View file

@ -29,7 +29,7 @@
#include <drivers/gpio/gpio_mmio32.h> #include <drivers/gpio/gpio_mmio32.h>
#include <errno.h> #include <errno.h>
static int gpio_mmio32_config(struct device *dev, int access_op, static int gpio_mmio32_config(struct device *dev,
u32_t pin, int flags) u32_t pin, int flags)
{ {
struct gpio_mmio32_context *context = dev->driver_data; struct gpio_mmio32_context *context = dev->driver_data;

31
drivers/gpio/gpio_nrfx.c
View file

@ -127,7 +127,7 @@ static int gpiote_pin_int_cfg(struct device *port, u32_t pin)
return res; return res;
} }
static int gpio_nrfx_config(struct device *port, int access_op, static int gpio_nrfx_config(struct device *port,
u32_t pin, int flags) u32_t pin, int flags)
{ {
NRF_GPIO_Type *reg = get_port_cfg(port)->port; NRF_GPIO_Type *reg = get_port_cfg(port)->port;
@ -135,8 +135,6 @@ static int gpio_nrfx_config(struct device *port, int access_op,
nrf_gpio_pin_drive_t drive; nrf_gpio_pin_drive_t drive;
nrf_gpio_pin_dir_t dir; nrf_gpio_pin_dir_t dir;
nrf_gpio_pin_input_t input; nrf_gpio_pin_input_t input;
u8_t from_pin;
u8_t to_pin;
switch (flags & (GPIO_DS_LOW_MASK | GPIO_DS_HIGH_MASK | switch (flags & (GPIO_DS_LOW_MASK | GPIO_DS_HIGH_MASK |
GPIO_OPEN_DRAIN)) { GPIO_OPEN_DRAIN)) {
@ -187,28 +185,17 @@ static int gpio_nrfx_config(struct device *port, int access_op,
? NRF_GPIO_PIN_INPUT_CONNECT ? NRF_GPIO_PIN_INPUT_CONNECT
: NRF_GPIO_PIN_INPUT_DISCONNECT; : NRF_GPIO_PIN_INPUT_DISCONNECT;
if (access_op == GPIO_ACCESS_BY_PORT) { if ((flags & GPIO_OUTPUT) != 0) {
from_pin = 0U; if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) {
to_pin = 31U; nrf_gpio_port_out_set(reg, BIT(pin));
} else { } else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0) {
from_pin = pin; nrf_gpio_port_out_clear(reg, BIT(pin));
to_pin = pin;
}
for (u8_t curr_pin = from_pin; curr_pin <= to_pin; ++curr_pin) {
if ((flags & GPIO_OUTPUT) != 0) {
if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) {
nrf_gpio_port_out_set(reg, BIT(curr_pin));
} else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0) {
nrf_gpio_port_out_clear(reg, BIT(curr_pin));
}
} }
nrf_gpio_cfg(NRF_GPIO_PIN_MAP(get_port_cfg(port)->port_num,
curr_pin),
dir, input, pull, drive, NRF_GPIO_PIN_NOSENSE);
} }
nrf_gpio_cfg(NRF_GPIO_PIN_MAP(get_port_cfg(port)->port_num, pin),
dir, input, pull, drive, NRF_GPIO_PIN_NOSENSE);
return 0; return 0;
} }

8
drivers/gpio/gpio_pca95xx.c
View file

@ -299,13 +299,12 @@ static int setup_pin_pullupdown(struct device *dev, u32_t pin, int flags)
* @brief Configure pin or port * @brief Configure pin or port
* *
* @param dev Device struct of the PCA95XX * @param dev Device struct of the PCA95XX
* @param access_op Access operation (pin or port)
* @param pin The pin number * @param pin The pin number
* @param flags Flags of pin or port * @param flags Flags of pin or port
* *
* @return 0 if successful, failed otherwise * @return 0 if successful, failed otherwise
*/ */
static int gpio_pca95xx_config(struct device *dev, int access_op, static int gpio_pca95xx_config(struct device *dev,
u32_t pin, int flags) u32_t pin, int flags)
{ {
int ret; int ret;
@ -318,11 +317,6 @@ static int gpio_pca95xx_config(struct device *dev, int access_op,
u16_t i2c_addr = config->i2c_slave_addr; u16_t i2c_addr = config->i2c_slave_addr;
#endif #endif
/* only support config by pin */
if (access_op != GPIO_ACCESS_BY_PIN) {
return -ENOTSUP;
}
/* Does not support disconnected pin */ /* Does not support disconnected pin */
if ((flags & (GPIO_INPUT | GPIO_OUTPUT)) == GPIO_DISCONNECTED) { if ((flags & (GPIO_INPUT | GPIO_OUTPUT)) == GPIO_DISCONNECTED) {
return -ENOTSUP; return -ENOTSUP;

59
drivers/gpio/gpio_rv32m1.c
View file

@ -70,7 +70,7 @@ static u32_t get_port_pcr_irqc_value_from_flags(struct device *dev,
} }
static int gpio_rv32m1_configure(struct device *dev, static int gpio_rv32m1_configure(struct device *dev,
int access_op, u32_t pin, int flags) u32_t pin, int flags)
{ {
const struct gpio_rv32m1_config *config = dev->config->config_info; const struct gpio_rv32m1_config *config = dev->config->config_info;
GPIO_Type *gpio_base = config->gpio_base; GPIO_Type *gpio_base = config->gpio_base;
@ -78,7 +78,6 @@ static int gpio_rv32m1_configure(struct device *dev,
struct gpio_rv32m1_data *data = dev->driver_data; struct gpio_rv32m1_data *data = dev->driver_data;
u32_t mask = 0U; u32_t mask = 0U;
u32_t pcr = 0U; u32_t pcr = 0U;
u8_t i;
/* Check for an invalid pin number */ /* Check for an invalid pin number */
if (pin >= ARRAY_SIZE(port_base->PCR)) { if (pin >= ARRAY_SIZE(port_base->PCR)) {
@ -111,28 +110,20 @@ static int gpio_rv32m1_configure(struct device *dev,
* 0 - pin is input, 1 - pin is output * 0 - pin is input, 1 - pin is output
*/ */
if (access_op == GPIO_ACCESS_BY_PIN) { switch (flags & GPIO_DIR_MASK) {
switch (flags & GPIO_DIR_MASK) { case GPIO_INPUT:
case GPIO_INPUT: gpio_base->PDDR &= ~BIT(pin);
gpio_base->PDDR &= ~BIT(pin); break;
break; case GPIO_OUTPUT:
case GPIO_OUTPUT: if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) {
if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) { gpio_base->PSOR = BIT(pin);
gpio_base->PSOR = BIT(pin); } else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0) {
} else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0) { gpio_base->PCOR = BIT(pin);
gpio_base->PCOR = BIT(pin);
}
gpio_base->PDDR |= BIT(pin);
break;
default:
return -ENOTSUP;
}
} else { /* GPIO_ACCESS_BY_PORT */
if ((flags & GPIO_INPUT) != 0) {
gpio_base->PDDR = 0x0;
} else { /* GPIO_OUTPUT */
gpio_base->PDDR = 0xFFFFFFFF;
} }
gpio_base->PDDR |= BIT(pin);
break;
default:
return -ENOTSUP;
} }
/* Now do the PORT module. Figure out the pullup/pulldown /* Now do the PORT module. Figure out the pullup/pulldown
@ -156,24 +147,10 @@ static int gpio_rv32m1_configure(struct device *dev,
*/ */
mask |= PORT_PCR_IRQC_MASK; mask |= PORT_PCR_IRQC_MASK;
/* Now we can write the PORT PCR register(s). If accessing by pin, we /* Accessing by pin, we only need to write one PCR register. */
* only need to write one PCR register. Otherwise, write all the PCR port_base->PCR[pin] = (port_base->PCR[pin] & ~mask) | pcr;
* registers in the PORT module (one for each pin). WRITE_BIT(data->pin_callback_enables, pin,
*/ flags & GPIO_INT_ENABLE);
if (access_op == GPIO_ACCESS_BY_PIN) {
port_base->PCR[pin] = (port_base->PCR[pin] & ~mask) | pcr;
WRITE_BIT(data->pin_callback_enables, pin,
flags & GPIO_INT_ENABLE);
} else { /* GPIO_ACCESS_BY_PORT */
for (i = 0U; i < ARRAY_SIZE(port_base->PCR); i++) {
port_base->PCR[i] = (port_base->PCR[pin] & ~mask) | pcr;
}
if (flags & GPIO_INT_ENABLE) {
data->pin_callback_enables = 0xFFFFFFFF;
} else {
data->pin_callback_enables = 0x0;
}
}
return 0; return 0;
} }

17
drivers/gpio/gpio_sam.c
View file

@ -132,23 +132,10 @@ static int gpio_sam_port_configure(struct device *dev, u32_t mask, int flags)
return 0; return 0;
} }
static int gpio_sam_config(struct device *dev, int access_op, u32_t pin, static int gpio_sam_config(struct device *dev, u32_t pin,
int flags) int flags)
{ {
int ret; return gpio_sam_port_configure(dev, BIT(pin), flags);
switch (access_op) {
case GPIO_ACCESS_BY_PIN:
ret = gpio_sam_port_configure(dev, BIT(pin), flags);
break;
case GPIO_ACCESS_BY_PORT:
ret = gpio_sam_port_configure(dev, GPIO_SAM_ALL_PINS, flags);
break;
default:
ret = -ENOTSUP;
}
return ret;
} }
static int gpio_sam_port_get_raw(struct device *dev, u32_t *value) static int gpio_sam_port_get_raw(struct device *dev, u32_t *value)

2
drivers/gpio/gpio_sam0.c
View file

@ -50,7 +50,7 @@ static void gpio_sam0_isr(u32_t pins, void *arg)
} }
#endif #endif
static int gpio_sam0_config(struct device *dev, int access_op, u32_t pin, static int gpio_sam0_config(struct device *dev, u32_t pin,
int flags) int flags)
{ {
const struct gpio_sam0_config *config = DEV_CFG(dev); const struct gpio_sam0_config *config = DEV_CFG(dev);

6
drivers/gpio/gpio_sifive.c
View file

@ -147,23 +147,17 @@ static void gpio_sifive_irq_handler(void *arg)
* @brief Configure pin * @brief Configure pin
* *
* @param dev Device structure * @param dev Device structure
* @param access_op Access operation
* @param pin The pin number * @param pin The pin number
* @param flags Flags of pin or port * @param flags Flags of pin or port
* *
* @return 0 if successful, failed otherwise * @return 0 if successful, failed otherwise
*/ */
static int gpio_sifive_config(struct device *dev, static int gpio_sifive_config(struct device *dev,
int access_op,
u32_t pin, u32_t pin,
int flags) int flags)
{ {
volatile struct gpio_sifive_t *gpio = DEV_GPIO(dev); volatile struct gpio_sifive_t *gpio = DEV_GPIO(dev);
if (access_op != GPIO_ACCESS_BY_PIN) {
return -ENOTSUP;
}
if (pin >= SIFIVE_PINMUX_PINS) { if (pin >= SIFIVE_PINMUX_PINS) {
return -EINVAL; return -EINVAL;
} }

7
drivers/gpio/gpio_stellaris.c
View file

@ -78,7 +78,7 @@ static void gpio_stellaris_isr(void *arg)
sys_write32(int_stat, GPIO_REG_ADDR(base, GPIO_ICR_OFFSET)); sys_write32(int_stat, GPIO_REG_ADDR(base, GPIO_ICR_OFFSET));
} }
static int gpio_stellaris_configure(struct device *dev, int access_op, static int gpio_stellaris_configure(struct device *dev,
u32_t pin, int flags) u32_t pin, int flags)
{ {
const struct gpio_stellaris_config *cfg = DEV_CFG(dev); const struct gpio_stellaris_config *cfg = DEV_CFG(dev);
@ -93,11 +93,6 @@ static int gpio_stellaris_configure(struct device *dev, int access_op,
return -ENOTSUP; return -ENOTSUP;
} }
/* Supports access by pin now,you can add access by port when needed */
if (access_op != GPIO_ACCESS_BY_PIN) {
return -EINVAL;
}
/* Check for pin availability */ /* Check for pin availability */
if (!sys_test_bit((u32_t)&port_map, pin)) { if (!sys_test_bit((u32_t)&port_map, pin)) {
return -EINVAL; return -EINVAL;

6
drivers/gpio/gpio_stm32.c
View file

@ -381,17 +381,13 @@ static int gpio_stm32_port_toggle_bits(struct device *dev,
/** /**
* @brief Configure pin or port * @brief Configure pin or port
*/ */
static int gpio_stm32_config(struct device *dev, int access_op, static int gpio_stm32_config(struct device *dev,
u32_t pin, int flags) u32_t pin, int flags)
{ {
const struct gpio_stm32_config *cfg = dev->config->config_info; const struct gpio_stm32_config *cfg = dev->config->config_info;
int err = 0; int err = 0;
int pincfg; int pincfg;
if (access_op != GPIO_ACCESS_BY_PIN) {
return -ENOTSUP;
}
#if defined(CONFIG_STM32H7_DUAL_CORE) #if defined(CONFIG_STM32H7_DUAL_CORE)
while (LL_HSEM_1StepLock(HSEM, LL_HSEM_ID_1)) { while (LL_HSEM_1StepLock(HSEM, LL_HSEM_ID_1)) {
} }

1
drivers/gpio/gpio_sx1509b.c
View file

@ -111,7 +111,6 @@ static inline int i2c_reg_write_word_be(struct device *dev, u16_t dev_addr,
} }
static int sx1509b_config(struct device *dev, static int sx1509b_config(struct device *dev,
int access_op, /* unused */
u32_t pin, u32_t pin,
int flags) int flags)
{ {

17
include/drivers/gpio.h
View file

@ -392,13 +392,6 @@ extern "C" {
/** @} */ /** @} */
/** @cond INTERNAL_HIDDEN */
#define GPIO_ACCESS_BY_PIN 0
#define GPIO_ACCESS_BY_PORT 1
/**
* @endcond
*/
/** /**
* @brief Identifies a set of pins associated with a port. * @brief Identifies a set of pins associated with a port.
* *
@ -551,7 +544,7 @@ enum gpio_int_trig {
}; };
struct gpio_driver_api { struct gpio_driver_api {
int (*config)(struct device *port, int access_op, u32_t pin, int flags); int (*config)(struct device *port, u32_t pin, int flags);
int (*port_get_raw)(struct device *port, gpio_port_value_t *value); int (*port_get_raw)(struct device *port, gpio_port_value_t *value);
int (*port_set_masked_raw)(struct device *port, gpio_port_pins_t mask, int (*port_set_masked_raw)(struct device *port, gpio_port_pins_t mask,
gpio_port_value_t value); gpio_port_value_t value);
@ -567,16 +560,16 @@ struct gpio_driver_api {
u32_t (*get_pending_int)(struct device *dev); u32_t (*get_pending_int)(struct device *dev);
}; };
__syscall int gpio_config(struct device *port, int access_op, u32_t pin, __syscall int gpio_config(struct device *port, u32_t pin,
gpio_flags_t flags); gpio_flags_t flags);
static inline int z_impl_gpio_config(struct device *port, int access_op, static inline int z_impl_gpio_config(struct device *port,
u32_t pin, gpio_flags_t flags) u32_t pin, gpio_flags_t flags)
{ {
const struct gpio_driver_api *api = const struct gpio_driver_api *api =
(const struct gpio_driver_api *)port->driver_api; (const struct gpio_driver_api *)port->driver_api;
return api->config(port, access_op, pin, (int)flags); return api->config(port, pin, (int)flags);
} }
__syscall int gpio_enable_callback(struct device *port, u32_t pin); __syscall int gpio_enable_callback(struct device *port, u32_t pin);
@ -754,7 +747,7 @@ static inline int gpio_pin_configure(struct device *port, u32_t pin,
__ASSERT((cfg->port_pin_mask & (gpio_port_pins_t)BIT(pin)) != 0U, __ASSERT((cfg->port_pin_mask & (gpio_port_pins_t)BIT(pin)) != 0U,
"Unsupported pin"); "Unsupported pin");
ret = gpio_config(port, GPIO_ACCESS_BY_PIN, pin, flags); ret = gpio_config(port, pin, flags);
if (ret != 0) { if (ret != 0) {
return ret; return ret;
} }