drivers: gpio: Xilinx PS MIO / EMIO GPIO driver
Driver implementation for the Xilinx Processor System MIO / EMIO GPIO controller as contained in the Zynq-7000 and ZynqMP (UltraScale) SoCs. The driver is split up into source and header for a parent controller device and source and header for 1..n child GPIO pin bank devices. The parent device driver takes care of IRQ handling, the GPIO pin bank driver provides pin / bank access according to the API defined by the GPIO subsystem. More than one device for this type of GPIO controller is required as it provides access to a number of GPIO pins well in excess of the 32 pins addressable by the current GPIO API (whereever parameters or return values come in the form of a bit mask): - Zynq-7000: 54 MIO GPIO pins, 64 EMIO GPIO pins in 4 banks. - ZynqMP: 78 MIO GPIO pins, 96 EMIO GPIO pins in 6 banks. Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
This commit is contained in:
Immo Birnbaum
Marti Bolivar
parent
cc95910957
commit
ca33905248
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@ -55,6 +55,7 @@ zephyr_library_sources_ifdef(CONFIG_GPIO_NCT38XX gpio_nct38xx_port.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_NCT38XX_INTERRUPT gpio_nct38xx_alert.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_TEST gpio_test.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_GD32 gpio_gd32.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_XLNX_PS gpio_xlnx_ps.c gpio_xlnx_ps_bank.c)
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zephyr_library_sources_ifdef(CONFIG_GPIO_SHELL gpio_shell.c)
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@ -121,4 +121,6 @@ source "drivers/gpio/Kconfig.test"
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source "drivers/gpio/Kconfig.gd32"
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source "drivers/gpio/Kconfig.xlnx_ps"
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endif # GPIO
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17
drivers/gpio/Kconfig.xlnx_ps
Normal file
17
drivers/gpio/Kconfig.xlnx_ps
Normal file
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@ -0,0 +1,17 @@
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#
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# Xilinx Processor System MIO / EMIO GPIO controller driver
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# configuration options
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#
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# Copyright (c) 2022, Weidmueller Interface GmbH & Co. KG
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# SPDX-License-Identifier: Apache-2.0
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#
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DT_COMPAT_XLNX_PS_GPIO := xlnx,ps-gpio
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config GPIO_XLNX_PS
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bool "Xilinx Processor System MIO / EMIO GPIO controller driver"
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default $(dt_compat_enabled,$(DT_COMPAT_XLNX_PS_GPIO))
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depends on SOC_XILINX_ZYNQMP_RPU || SOC_FAMILY_XILINX_ZYNQ7000
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depends on !QEMU_TARGET
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help
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Enable the Xilinx Processor System MIO / EMIO GPIO controller driver.
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151
drivers/gpio/gpio_xlnx_ps.c
Normal file
151
drivers/gpio/gpio_xlnx_ps.c
Normal file
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@ -0,0 +1,151 @@
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/*
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* Xilinx Processor System MIO / EMIO GPIO controller driver
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* Parent (IRQ handler) module
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*
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* Copyright (c) 2022, Weidmueller Interface GmbH & Co. KG
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <devicetree.h>
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#include <drivers/gpio.h>
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#include "gpio_utils.h"
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#include "gpio_xlnx_ps.h"
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#include "gpio_xlnx_ps_bank.h"
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#define LOG_MODULE_NAME gpio_xlnx_ps
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#define LOG_LEVEL CONFIG_GPIO_LOG_LEVEL
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#include <logging/log.h>
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LOG_MODULE_REGISTER(LOG_MODULE_NAME);
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#define DT_DRV_COMPAT xlnx_ps_gpio
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/*
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* An API is required for this driver, but as no pin access is provided at
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* this level, use the default API contents provided by the driver subsystem.
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*/
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static const struct gpio_driver_api gpio_xlnx_ps_default_apis;
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/**
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* @brief Initialize a Xilinx PS GPIO controller parent device
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*
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* Initialize a Xilinx PS GPIO controller parent device, whose task it is
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* to handle the IRQ line of each controller instance, while the configuration,
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* status and data acquisition of each MIO / EMIO GPIO pin associated with
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* the parent controller instance is handled via the respective GPIO pin
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* bank's child device.
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*
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* @param dev Pointer to the PS GPIO controller's device.
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*
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* @retval Always 0.
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*/
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static int gpio_xlnx_ps_init(const struct device *dev)
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{
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const struct gpio_xlnx_ps_dev_cfg *dev_conf = dev->config;
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/* Initialize the device's interrupt */
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dev_conf->config_func(dev);
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return 0;
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}
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/**
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* @brief Xilinx PS GPIO controller parent device ISR
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*
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* Interrupt service routine for the Xilinx PS GPIO controller's
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* IRQ. The ISR iterates all associated MIO / EMIO GPIO pink bank
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* child device instances and checks each bank's interrupt status.
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* If any pending interrupt is detected within a GPIO pin bank,
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* the callbacks registered for the respective bank are triggered
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* using the functionality provided by the GPIO sub-system.
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*
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* @param dev Pointer to the PS GPIO controller's device.
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*/
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static void gpio_xlnx_ps_isr(const struct device *dev)
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{
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const struct gpio_xlnx_ps_dev_cfg *dev_conf = dev->config;
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const struct gpio_driver_api *api;
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struct gpio_xlnx_ps_bank_dev_data *bank_data;
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uint32_t bank;
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uint32_t int_mask;
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for (bank = 0; bank < dev_conf->num_banks; bank++) {
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api = dev_conf->bank_devices[bank]->api;
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int_mask = 0;
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if (api != NULL) {
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int_mask = api->get_pending_int(dev_conf->bank_devices[bank]);
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}
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if (int_mask) {
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bank_data = (struct gpio_xlnx_ps_bank_dev_data *)
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dev_conf->bank_devices[bank]->data;
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gpio_fire_callbacks(&bank_data->callbacks,
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dev_conf->bank_devices[bank], int_mask);
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}
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}
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}
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/* Device definition macros */
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/*
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* Macros generating a list of all associated GPIO pin bank child
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* devices for the parent controller device's config data struct
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* specified in the device tree.
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*/
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#define GPIO_XLNX_PS_CHILD_CONCAT(idx) DEVICE_DT_GET(idx),
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#define GPIO_XLNX_PS_GEN_BANK_ARRAY(idx)\
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static const struct device *gpio_xlnx_ps##idx##_banks[] = {\
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DT_FOREACH_CHILD_STATUS_OKAY(DT_DRV_INST(idx), GPIO_XLNX_PS_CHILD_CONCAT)\
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};
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/* Device config & run-time data struct creation macros */
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#define GPIO_XLNX_PS_DEV_DATA(idx)\
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static struct gpio_xlnx_ps_dev_data gpio_xlnx_ps##idx##_data;
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#define GPIO_XLNX_PS_DEV_CONFIG(idx)\
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static const struct gpio_xlnx_ps_dev_cfg gpio_xlnx_ps##idx##_cfg = {\
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.base_addr = DT_INST_REG_ADDR(idx),\
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.bank_devices = gpio_xlnx_ps##idx##_banks,\
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.num_banks = ARRAY_SIZE(gpio_xlnx_ps##idx##_banks),\
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.config_func = gpio_xlnx_ps##idx##_irq_config\
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};
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/*
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* Macro used to generate each parent controller device's IRQ attach
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* function.
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*/
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#define GPIO_XLNX_PS_DEV_CONFIG_IRQ_FUNC(idx)\
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static void gpio_xlnx_ps##idx##_irq_config(const struct device *dev)\
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{\
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ARG_UNUSED(dev);\
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IRQ_CONNECT(DT_INST_IRQN(idx), DT_INST_IRQ(idx, priority),\
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gpio_xlnx_ps_isr, DEVICE_DT_INST_GET(idx), 0);\
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irq_enable(DT_INST_IRQN(idx));\
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}
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/* Device definition macro */
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#define GPIO_XLNX_PS_DEV_DEFINE(idx)\
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DEVICE_DT_INST_DEFINE(idx, gpio_xlnx_ps_init, NULL,\
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&gpio_xlnx_ps##idx##_data, &gpio_xlnx_ps##idx##_cfg,\
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PRE_KERNEL_2, CONFIG_GPIO_INIT_PRIORITY, &gpio_xlnx_ps_default_apis);
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/*
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* Top-level device initialization macro, executed for each PS GPIO
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* parent device entry contained in the device tree which has status
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* "okay".
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*/
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#define GPIO_XLNX_PS_DEV_INITITALIZE(idx)\
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GPIO_XLNX_PS_GEN_BANK_ARRAY(idx)\
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GPIO_XLNX_PS_DEV_CONFIG_IRQ_FUNC(idx)\
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GPIO_XLNX_PS_DEV_DATA(idx)\
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GPIO_XLNX_PS_DEV_CONFIG(idx)\
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GPIO_XLNX_PS_DEV_DEFINE(idx)
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/*
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* Register & initialize all instances of the Processor System's MIO / EMIO GPIO
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* controller specified in the device tree.
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*/
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DT_INST_FOREACH_STATUS_OKAY(GPIO_XLNX_PS_DEV_INITITALIZE);
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45
drivers/gpio/gpio_xlnx_ps.h
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45
drivers/gpio/gpio_xlnx_ps.h
Normal file
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@ -0,0 +1,45 @@
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/*
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* Xilinx Processor System MIO / EMIO GPIO controller driver
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*
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* Driver private data declarations, parent (IRQ handler) module
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*
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* Copyright (c) 2022, Weidmueller Interface GmbH & Co. KG
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _ZEPHYR_DRIVERS_GPIO_GPIO_XLNX_PS_H_
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#define _ZEPHYR_DRIVERS_GPIO_GPIO_XLNX_PS_H_
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/* Type definitions */
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/* IRQ handler function type */
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typedef void (*gpio_xlnx_ps_config_irq_t)(const struct device *dev);
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/**
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* @brief Run-time modifiable device data structure.
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*
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* This struct contains all data of the PS GPIO controller parent
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* (IRQ handler) which is modifiable at run-time.
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*/
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struct gpio_xlnx_ps_dev_data {
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struct gpio_driver_data common;
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};
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/**
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* @brief Constant device configuration data structure.
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*
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* This struct contains all data of the PS GPIO controller parent
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* which is required for proper operation (such as base memory
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* addresses, references to all associated banks etc.) which don't
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* have to and therefore cannot be modified at run-time.
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*/
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struct gpio_xlnx_ps_dev_cfg {
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struct gpio_driver_config common;
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uint32_t base_addr;
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const struct device **bank_devices;
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uint32_t num_banks;
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gpio_xlnx_ps_config_irq_t config_func;
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};
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#endif /* _ZEPHYR_DRIVERS_GPIO_GPIO_XLNX_PS_H_ */
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447
drivers/gpio/gpio_xlnx_ps_bank.c
Normal file
447
drivers/gpio/gpio_xlnx_ps_bank.c
Normal file
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@ -0,0 +1,447 @@
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/*
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* Xilinx Processor System MIO / EMIO GPIO controller driver
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* GPIO bank module
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*
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* Copyright (c) 2022, Weidmueller Interface GmbH & Co. KG
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <device.h>
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#include <devicetree.h>
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#include <drivers/gpio.h>
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#include "gpio_utils.h"
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#include "gpio_xlnx_ps_bank.h"
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#define LOG_MODULE_NAME gpio_xlnx_ps_bank
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#define LOG_LEVEL CONFIG_GPIO_LOG_LEVEL
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#include <logging/log.h>
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LOG_MODULE_REGISTER(LOG_MODULE_NAME);
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#define DT_DRV_COMPAT xlnx_ps_gpio_bank
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/**
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* @brief GPIO bank pin configuration function
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*
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* Configures an individual pin within a MIO / EMIO GPIO pin bank.
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* The following flags specified by the GPIO subsystem are NOT
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* supported by the PS GPIO controller:
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*
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* - Pull up
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* - Pull down
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* - Open drain
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* - Open source.
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*
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* @param dev Pointer to the GPIO bank's device.
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* @param pin Index of the pin within the bank to be configured
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* (decimal index of the pin).
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* @param flags Flags specifying the pin's configuration.
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*
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* @retval 0 if the device initialization completed successfully,
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* -EINVAL if the specified pin index is out of range,
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* -ENOTSUP if the pin configuration data contains a flag
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* that is not supported by the controller.
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*/
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static int gpio_xlnx_ps_pin_configure(const struct device *dev,
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gpio_pin_t pin,
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gpio_flags_t flags)
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{
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const struct gpio_xlnx_ps_bank_dev_cfg *dev_conf = dev->config;
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uint32_t pin_mask = BIT(pin);
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uint32_t bank_data;
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uint32_t dirm_data;
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uint32_t oen_data;
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/* Validity of the specified pin index is checked in drivers/gpio.h */
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/* Check for config flags not supported by the controller */
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if (flags & (GPIO_PULL_UP | GPIO_PULL_DOWN | GPIO_SINGLE_ENDED)) {
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return -ENOTSUP;
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}
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/* Read the data direction & output enable registers */
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dirm_data = sys_read32(GPIO_XLNX_PS_BANK_DIRM_REG);
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oen_data = sys_read32(GPIO_XLNX_PS_BANK_OEN_REG);
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if (flags & GPIO_OUTPUT) {
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dirm_data |= pin_mask;
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oen_data |= pin_mask;
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/*
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* Setting of an initial value (see below) requires the
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* direction register to be written *BEFORE* the data
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* register, otherwise, the value will not be applied!
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* The output enable bit can be set after the initial
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* value has been written.
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*/
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sys_write32(dirm_data, GPIO_XLNX_PS_BANK_DIRM_REG);
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/*
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* If the current pin is to be configured as an output
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* pin, it is up to the caller to specify whether the
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* output's initial value shall be high or low.
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* -> Write the initial output value into the data register.
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*/
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bank_data = sys_read32(GPIO_XLNX_PS_BANK_DATA_REG);
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if (flags & GPIO_OUTPUT_INIT_HIGH) {
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bank_data |= pin_mask;
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} else if (flags & GPIO_OUTPUT_INIT_LOW) {
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bank_data &= ~pin_mask;
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}
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sys_write32(bank_data, GPIO_XLNX_PS_BANK_DATA_REG);
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/* Set the pin's output enable bit */
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sys_write32(oen_data, GPIO_XLNX_PS_BANK_OEN_REG);
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} else {
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dirm_data &= ~pin_mask;
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oen_data &= ~pin_mask;
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/*
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* Disable the output first in case of an O -> I
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* transition, then change the pin's direction.
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*/
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sys_write32(oen_data, GPIO_XLNX_PS_BANK_OEN_REG);
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sys_write32(dirm_data, GPIO_XLNX_PS_BANK_DIRM_REG);
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}
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return 0;
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}
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/**
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* @brief Reads the current bit mask of the entire GPIO pin bank.
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*
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* Reads the current bit mask of the entire bank from the
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* read-only data register. This includes the current values
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* of not just all input pins, but both the input and output
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* pins within the bank.
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*
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* @param dev Pointer to the GPIO bank's device.
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* @param value Pointer to a variable of type gpio_port_value_t
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* to which the current bit mask read from the bank's
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* RO data register will be written to.
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*
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* @retval 0 if the read operation completed successfully,
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* -EINVAL if the pointer to the output variable is NULL.
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*/
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static int gpio_xlnx_ps_bank_get(const struct device *dev,
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gpio_port_value_t *value)
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{
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const struct gpio_xlnx_ps_bank_dev_cfg *dev_conf = dev->config;
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*value = sys_read32(GPIO_XLNX_PS_BANK_DATA_REG);
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return 0;
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}
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/**
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* @brief Masked write of a bit mask for the entire GPIO pin bank.
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*
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* Performs a masked write operation on the data register of
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* the current GPIO pin bank. The mask is applied twice:
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* first, it is applied to the current contents of the bank's
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* RO data register, clearing any bits that are zeroes in the
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* mask (will not have any effect on input pins). Second, it
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* is applied to the data word to be written into the current
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* bank's data register. The masked data word read from the
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* RO data register and the masked data word provided by the
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* caller ar then OR'ed and written to the bank's data register.
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*
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* @param dev Pointer to the GPIO bank's device.
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* @param mask Mask to be applied to both the current contents
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* of the data register and the data word provided
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* by the caller.
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* @param value Value to be written to the current bank's data
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* register.
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*
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* @retval Always 0.
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*/
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static int gpio_xlnx_ps_bank_set_masked(const struct device *dev,
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gpio_port_pins_t mask,
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gpio_port_value_t value)
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{
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const struct gpio_xlnx_ps_bank_dev_cfg *dev_conf = dev->config;
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uint32_t bank_data;
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bank_data = sys_read32(GPIO_XLNX_PS_BANK_DATA_REG);
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bank_data = (bank_data & ~mask) | (value & mask);
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sys_write32(bank_data, GPIO_XLNX_PS_BANK_DATA_REG);
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return 0;
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}
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/**
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* @brief Sets bits in the data register of the GPIO pin bank.
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*
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* Sets bits in the data register of the current GPIO pin bank
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* as a read-modify-write operation. All bits set in the bit
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* mask provided by the caller are OR'ed into the current data
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* word of the bank. This operation has no effect on the values
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* associated with pins configured as inputs.
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*
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* @param dev Pointer to the GPIO bank's device.
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* @param pins Bit mask specifying which bits shall be set in
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* the data word of the current GPIO pin bank.
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*
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* @retval Always 0.
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*/
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static int gpio_xlnx_ps_bank_set_bits(const struct device *dev,
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||||
gpio_port_pins_t pins)
|
||||
{
|
||||
const struct gpio_xlnx_ps_bank_dev_cfg *dev_conf = dev->config;
|
||||
uint32_t bank_data;
|
||||
|
||||
bank_data = sys_read32(GPIO_XLNX_PS_BANK_DATA_REG);
|
||||
bank_data |= pins;
|
||||
sys_write32(bank_data, GPIO_XLNX_PS_BANK_DATA_REG);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears bits in the data register of the GPIO pin bank.
|
||||
*
|
||||
* Clears bits in the data register of the current GPIO pin bank
|
||||
* as a read-modify-write operation. All bits set in the bit
|
||||
* mask provided by the caller are NAND'ed into the current data
|
||||
* word of the bank. This operation has no effect on the values
|
||||
* associated with pins configured as inputs.
|
||||
*
|
||||
* @param dev Pointer to the GPIO bank's device.
|
||||
* @param pins Bit mask specifying which bits shall be cleared
|
||||
* in the data word of the current GPIO pin bank.
|
||||
*
|
||||
* @retval Always 0.
|
||||
*/
|
||||
static int gpio_xlnx_ps_bank_clear_bits(const struct device *dev,
|
||||
gpio_port_pins_t pins)
|
||||
{
|
||||
const struct gpio_xlnx_ps_bank_dev_cfg *dev_conf = dev->config;
|
||||
uint32_t bank_data;
|
||||
|
||||
bank_data = sys_read32(GPIO_XLNX_PS_BANK_DATA_REG);
|
||||
bank_data &= ~pins;
|
||||
sys_write32(bank_data, GPIO_XLNX_PS_BANK_DATA_REG);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Toggles bits in the data register of the GPIO pin bank.
|
||||
*
|
||||
* Toggles bits in the data register of the current GPIO pin bank
|
||||
* as a read-modify-write operation. All bits set in the bit
|
||||
* mask provided by the caller are XOR'ed into the current data
|
||||
* word of the bank. This operation has no effect on the values
|
||||
* associated with pins configured as inputs.
|
||||
*
|
||||
* @param dev Pointer to the GPIO bank's device.
|
||||
* @param pins Bit mask specifying which bits shall be toggled
|
||||
* in the data word of the current GPIO pin bank.
|
||||
*
|
||||
* @retval Always 0.
|
||||
*/
|
||||
static int gpio_xlnx_ps_bank_toggle_bits(const struct device *dev,
|
||||
gpio_port_pins_t pins)
|
||||
{
|
||||
const struct gpio_xlnx_ps_bank_dev_cfg *dev_conf = dev->config;
|
||||
uint32_t bank_data;
|
||||
|
||||
bank_data = sys_read32(GPIO_XLNX_PS_BANK_DATA_REG);
|
||||
bank_data ^= pins;
|
||||
sys_write32(bank_data, GPIO_XLNX_PS_BANK_DATA_REG);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the interrupt behaviour of a pin within the
|
||||
* current GPIO bank.
|
||||
*
|
||||
* Configures the interrupt behaviour of a pin within the current
|
||||
* GPIO bank. If a pin is to be configured to trigger an interrupt,
|
||||
* the following modes are supported:
|
||||
*
|
||||
* - edge or level triggered,
|
||||
* - rising edge / high level or falling edge / low level,
|
||||
* - in edge mode only: trigger on both rising and falling edge.
|
||||
*
|
||||
* @param dev Pointer to the GPIO bank's device.
|
||||
* @param pin Index of the pin within the bank to be configured
|
||||
* (decimal index of the pin).
|
||||
* @param mode Mode configuration: edge, level or interrupt disabled.
|
||||
* @param trig Trigger condition configuration: high/low level or
|
||||
* rising/falling/both edge(s).
|
||||
*
|
||||
* @retval 0 if the interrupt configuration completed successfully,
|
||||
* -EINVAL if the specified pin index is out of range,
|
||||
* -ENOTSUP if the interrupt configuration data contains an
|
||||
* invalid combination of configuration flags.
|
||||
*/
|
||||
static int gpio_xlnx_ps_bank_pin_irq_configure(const struct device *dev,
|
||||
gpio_pin_t pin,
|
||||
enum gpio_int_mode mode,
|
||||
enum gpio_int_trig trig)
|
||||
{
|
||||
const struct gpio_xlnx_ps_bank_dev_cfg *dev_conf = dev->config;
|
||||
uint32_t pin_mask = BIT(pin);
|
||||
uint32_t int_type_data;
|
||||
uint32_t int_polarity_data;
|
||||
uint32_t int_any_data;
|
||||
|
||||
/* Validity of the specified pin index is checked in drivers/gpio.h */
|
||||
|
||||
/* Disable the specified pin's interrupt before (re-)configuring it */
|
||||
sys_write32(pin_mask, GPIO_XLNX_PS_BANK_INT_DIS_REG);
|
||||
|
||||
int_type_data = sys_read32(GPIO_XLNX_PS_BANK_INT_TYPE_REG);
|
||||
int_polarity_data = sys_read32(GPIO_XLNX_PS_BANK_INT_POLARITY_REG);
|
||||
int_any_data = sys_read32(GPIO_XLNX_PS_BANK_INT_ANY_REG);
|
||||
|
||||
if (mode != GPIO_INT_MODE_DISABLED) {
|
||||
|
||||
if (mode == GPIO_INT_MODE_LEVEL) {
|
||||
int_type_data &= ~pin_mask;
|
||||
} else if (mode == GPIO_INT_MODE_EDGE) {
|
||||
int_type_data |= pin_mask;
|
||||
} else {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (trig == GPIO_INT_TRIG_LOW) {
|
||||
int_any_data &= ~pin_mask;
|
||||
int_polarity_data &= ~pin_mask;
|
||||
} else if (trig == GPIO_INT_TRIG_HIGH) {
|
||||
int_any_data &= ~pin_mask;
|
||||
int_polarity_data |= pin_mask;
|
||||
} else if (trig == GPIO_INT_TRIG_BOTH) {
|
||||
if (mode == GPIO_INT_MODE_LEVEL) {
|
||||
return -EINVAL;
|
||||
}
|
||||
int_any_data |= pin_mask;
|
||||
}
|
||||
|
||||
} else { /* mode == GPIO_INT_MODE_DISABLED */
|
||||
int_any_data &= ~pin_mask;
|
||||
int_polarity_data &= ~pin_mask;
|
||||
int_type_data &= ~pin_mask;
|
||||
}
|
||||
|
||||
sys_write32(int_any_data, GPIO_XLNX_PS_BANK_INT_ANY_REG);
|
||||
sys_write32(int_polarity_data, GPIO_XLNX_PS_BANK_INT_POLARITY_REG);
|
||||
sys_write32(int_type_data, GPIO_XLNX_PS_BANK_INT_TYPE_REG);
|
||||
|
||||
if (mode != GPIO_INT_MODE_DISABLED) {
|
||||
/* Clear potential stale pending bit before enabling interrupt */
|
||||
sys_write32(pin_mask, GPIO_XLNX_PS_BANK_INT_STAT_REG);
|
||||
sys_write32(pin_mask, GPIO_XLNX_PS_BANK_INT_EN_REG);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the interrupt status of the current GPIO bank.
|
||||
*
|
||||
* Returns the interrupt status of the current GPIO bank, in the
|
||||
* form of a bit mask where each pin with a pending interrupt is
|
||||
* indicated. This information can either be used by the PM sub-
|
||||
* system or the parent controller device driver, which manages
|
||||
* the interrupt line of the entire PS GPIO controller, regardless
|
||||
* of how many bank sub-devices exist. As the current status is
|
||||
* read, it is automatically cleared. Callback triggering is handled
|
||||
* by the parent controller device.
|
||||
*
|
||||
* @param dev Pointer to the GPIO bank's device.
|
||||
*
|
||||
* @retval A bit mask indicating for which pins within the bank
|
||||
* an interrupt is pending.
|
||||
*/
|
||||
static uint32_t gpio_xlnx_ps_bank_get_int_status(const struct device *dev)
|
||||
{
|
||||
const struct gpio_xlnx_ps_bank_dev_cfg *dev_conf = dev->config;
|
||||
uint32_t int_status;
|
||||
|
||||
int_status = sys_read32(GPIO_XLNX_PS_BANK_INT_STAT_REG);
|
||||
if (int_status != 0) {
|
||||
sys_write32(int_status, GPIO_XLNX_PS_BANK_INT_STAT_REG);
|
||||
}
|
||||
|
||||
return int_status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Callback management re-direction function.
|
||||
*
|
||||
* Re-directs any callback management calls relating to the current
|
||||
* GPIO bank to the GPIO sub-system. Comp. documentation of the
|
||||
* underlying sub-system's #gpio_manage_callback function.
|
||||
*
|
||||
* @param dev Pointer to the GPIO bank's device.
|
||||
* @param callback Pointer to a GPIO callback struct.
|
||||
* @param set Callback set flag.
|
||||
*
|
||||
* @retval A bit mask indicating for which pins within the bank
|
||||
* an interrupt is pending.
|
||||
*/
|
||||
static int gpio_xlnx_ps_bank_manage_callback(const struct device *dev,
|
||||
struct gpio_callback *callback,
|
||||
bool set)
|
||||
{
|
||||
struct gpio_xlnx_ps_bank_dev_data *dev_data = dev->data;
|
||||
|
||||
return gpio_manage_callback(&dev_data->callbacks, callback, set);
|
||||
}
|
||||
|
||||
/* GPIO bank device driver API */
|
||||
static const struct gpio_driver_api gpio_xlnx_ps_bank_apis = {
|
||||
.pin_configure = gpio_xlnx_ps_pin_configure,
|
||||
.port_get_raw = gpio_xlnx_ps_bank_get,
|
||||
.port_set_masked_raw = gpio_xlnx_ps_bank_set_masked,
|
||||
.port_set_bits_raw = gpio_xlnx_ps_bank_set_bits,
|
||||
.port_clear_bits_raw = gpio_xlnx_ps_bank_clear_bits,
|
||||
.port_toggle_bits = gpio_xlnx_ps_bank_toggle_bits,
|
||||
.pin_interrupt_configure = gpio_xlnx_ps_bank_pin_irq_configure,
|
||||
.manage_callback = gpio_xlnx_ps_bank_manage_callback,
|
||||
.get_pending_int = gpio_xlnx_ps_bank_get_int_status
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief Initialize a MIO / EMIO GPIO bank sub-device
|
||||
*
|
||||
* Initialize a MIO / EMIO GPIO bank sub-device, which is a child
|
||||
* of the parent Xilinx PS GPIO controller device driver. This ini-
|
||||
* tialization function sets up a defined initial state for each
|
||||
* GPIO bank.
|
||||
*
|
||||
* @param dev Pointer to the GPIO bank's device.
|
||||
*
|
||||
* @retval Always 0.
|
||||
*/
|
||||
static int gpio_xlnx_ps_bank_init(const struct device *dev)
|
||||
{
|
||||
const struct gpio_xlnx_ps_bank_dev_cfg *dev_conf = dev->config;
|
||||
|
||||
sys_write32(~0x0, GPIO_XLNX_PS_BANK_INT_DIS_REG); /* Disable all interrupts */
|
||||
sys_write32(~0x0, GPIO_XLNX_PS_BANK_INT_STAT_REG); /* Clear all interrupts */
|
||||
sys_write32(0x0, GPIO_XLNX_PS_BANK_OEN_REG); /* All outputs disabled */
|
||||
sys_write32(0x0, GPIO_XLNX_PS_BANK_DIRM_REG); /* All pins input */
|
||||
sys_write32(0x0, GPIO_XLNX_PS_BANK_DATA_REG); /* Zero data register */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* MIO / EMIO bank device definition macros */
|
||||
#define GPIO_XLNX_PS_BANK_INIT(idx)\
|
||||
static const struct gpio_xlnx_ps_bank_dev_cfg gpio_xlnx_ps_bank##idx##_cfg = {\
|
||||
.common = {\
|
||||
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(idx),\
|
||||
},\
|
||||
.base_addr = DT_REG_ADDR(DT_PARENT(DT_INST(idx, DT_DRV_COMPAT))),\
|
||||
.bank_index = idx,\
|
||||
};\
|
||||
static struct gpio_xlnx_ps_bank_dev_data gpio_xlnx_ps_bank##idx##_data;\
|
||||
DEVICE_DT_INST_DEFINE(idx, gpio_xlnx_ps_bank_init, NULL,\
|
||||
&gpio_xlnx_ps_bank##idx##_data, &gpio_xlnx_ps_bank##idx##_cfg,\
|
||||
PRE_KERNEL_1, CONFIG_GPIO_INIT_PRIORITY, &gpio_xlnx_ps_bank_apis);
|
||||
|
||||
/* Register & initialize all MIO / EMIO GPIO banks specified in the device tree. */
|
||||
DT_INST_FOREACH_STATUS_OKAY(GPIO_XLNX_PS_BANK_INIT);
|
||||
72
drivers/gpio/gpio_xlnx_ps_bank.h
Normal file
72
drivers/gpio/gpio_xlnx_ps_bank.h
Normal file
|
|
@ -0,0 +1,72 @@
|
|||
/*
|
||||
* Xilinx Processor System MIO / EMIO GPIO controller driver
|
||||
*
|
||||
* Driver private data declarations, GPIO bank module
|
||||
*
|
||||
* Copyright (c) 2022, Weidmueller Interface GmbH & Co. KG
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef _ZEPHYR_DRIVERS_GPIO_GPIO_XLNX_PS_BANK_H_
|
||||
#define _ZEPHYR_DRIVERS_GPIO_GPIO_XLNX_PS_BANK_H_
|
||||
|
||||
/*
|
||||
* Register address calculation macros
|
||||
* Register address offsets: comp. Zynq-7000 TRM, ug585, chap. B.19
|
||||
*/
|
||||
#define GPIO_XLNX_PS_BANK_MASK_DATA_LSW_REG (dev_conf->base_addr\
|
||||
+ ((uint32_t)dev_conf->bank_index * 0x8))
|
||||
#define GPIO_XLNX_PS_BANK_MASK_DATA_MSW_REG ((dev_conf->base_addr + 0x04)\
|
||||
+ ((uint32_t)dev_conf->bank_index * 0x8))
|
||||
#define GPIO_XLNX_PS_BANK_DATA_REG ((dev_conf->base_addr + 0x40)\
|
||||
+ ((uint32_t)dev_conf->bank_index * 0x4))
|
||||
#define GPIO_XLNX_PS_BANK_DATA_RO_REG ((dev_conf->base_addr + 0x60)\
|
||||
+ ((uint32_t)dev_conf->bank_index * 0x4))
|
||||
#define GPIO_XLNX_PS_BANK_DIRM_REG ((dev_conf->base_addr + 0x204)\
|
||||
+ ((uint32_t)dev_conf->bank_index * 0x40))
|
||||
#define GPIO_XLNX_PS_BANK_OEN_REG ((dev_conf->base_addr + 0x208)\
|
||||
+ ((uint32_t)dev_conf->bank_index * 0x40))
|
||||
#define GPIO_XLNX_PS_BANK_INT_MASK_REG ((dev_conf->base_addr + 0x20C)\
|
||||
+ ((uint32_t)dev_conf->bank_index * 0x40))
|
||||
#define GPIO_XLNX_PS_BANK_INT_EN_REG ((dev_conf->base_addr + 0x210)\
|
||||
+ ((uint32_t)dev_conf->bank_index * 0x40))
|
||||
#define GPIO_XLNX_PS_BANK_INT_DIS_REG ((dev_conf->base_addr + 0x214)\
|
||||
+ ((uint32_t)dev_conf->bank_index * 0x40))
|
||||
#define GPIO_XLNX_PS_BANK_INT_STAT_REG ((dev_conf->base_addr + 0x218)\
|
||||
+ ((uint32_t)dev_conf->bank_index * 0x40))
|
||||
#define GPIO_XLNX_PS_BANK_INT_TYPE_REG ((dev_conf->base_addr + 0x21C)\
|
||||
+ ((uint32_t)dev_conf->bank_index * 0x40))
|
||||
#define GPIO_XLNX_PS_BANK_INT_POLARITY_REG ((dev_conf->base_addr + 0x220)\
|
||||
+ ((uint32_t)dev_conf->bank_index * 0x40))
|
||||
#define GPIO_XLNX_PS_BANK_INT_ANY_REG ((dev_conf->base_addr + 0x224)\
|
||||
+ ((uint32_t)dev_conf->bank_index * 0x40))
|
||||
|
||||
/**
|
||||
* @brief Run-time modifiable device data structure.
|
||||
*
|
||||
* This struct contains all data of a PS MIO / EMIO GPIO bank
|
||||
* which is modifiable at run-time, such as the configuration
|
||||
* parameters and current values of each individual pin belonging
|
||||
* to the respective bank.
|
||||
*/
|
||||
struct gpio_xlnx_ps_bank_dev_data {
|
||||
struct gpio_driver_data common;
|
||||
sys_slist_t callbacks;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief Constant device configuration data structure.
|
||||
*
|
||||
* This struct contains all data of a PS MIO / EMIO GPIO bank
|
||||
* which is required for proper operation (such as base memory
|
||||
* addresses etc.) which don't have to and therefore cannot be
|
||||
* modified at run-time.
|
||||
*/
|
||||
struct gpio_xlnx_ps_bank_dev_cfg {
|
||||
struct gpio_driver_config common;
|
||||
|
||||
uint32_t base_addr;
|
||||
uint8_t bank_index;
|
||||
};
|
||||
|
||||
#endif /* _ZEPHYR_DRIVERS_GPIO_GPIO_XLNX_PS_BANK_H_ */
|
||||
Loading…
Reference in a new issue