ca33905248
Driver implementation for the Xilinx Processor System MIO / EMIO GPIO controller as contained in the Zynq-7000 and ZynqMP (UltraScale) SoCs. The driver is split up into source and header for a parent controller device and source and header for 1..n child GPIO pin bank devices. The parent device driver takes care of IRQ handling, the GPIO pin bank driver provides pin / bank access according to the API defined by the GPIO subsystem. More than one device for this type of GPIO controller is required as it provides access to a number of GPIO pins well in excess of the 32 pins addressable by the current GPIO API (whereever parameters or return values come in the form of a bit mask): - Zynq-7000: 54 MIO GPIO pins, 64 EMIO GPIO pins in 4 banks. - ZynqMP: 78 MIO GPIO pins, 96 EMIO GPIO pins in 6 banks. Signed-off-by: Immo Birnbaum <Immo.Birnbaum@weidmueller.com>
18 lines
537 B
Plaintext
18 lines
537 B
Plaintext
#
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# Xilinx Processor System MIO / EMIO GPIO controller driver
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# configuration options
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#
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# Copyright (c) 2022, Weidmueller Interface GmbH & Co. KG
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# SPDX-License-Identifier: Apache-2.0
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#
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DT_COMPAT_XLNX_PS_GPIO := xlnx,ps-gpio
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config GPIO_XLNX_PS
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bool "Xilinx Processor System MIO / EMIO GPIO controller driver"
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default $(dt_compat_enabled,$(DT_COMPAT_XLNX_PS_GPIO))
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depends on SOC_XILINX_ZYNQMP_RPU || SOC_FAMILY_XILINX_ZYNQ7000
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depends on !QEMU_TARGET
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help
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Enable the Xilinx Processor System MIO / EMIO GPIO controller driver.
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