dts: x86: Add dts support for x86

patch adds necessary files and does the modification to the existing
files to add device support for x86 based intel quark microcontroller

Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com>

arch/x86/core/Kconfig

@@ -50,17 +50,21 @@ config MAX_IRQ_LINES
 	to program to the PIC the association between vectors and
 	interrupts.
 
+if !HAS_DTS
 config PHYS_LOAD_ADDR
 	hex "Physical load address"
 	# Default value must be supplied by platform
 	help
 	This option specifies the physical address where the kernel is loaded.
+endif
 
+if !HAS_DTS
 config PHYS_RAM_ADDR
 	hex "Physical RAM address"
 	# Default value must be supplied by platform
 	help
 	This option specifies the physical RAM address of the selected SoC.
+endif
 
 config RAM_SIZE
 	int "Amount of RAM given to the kernel (in kB)"

arch/x86/soc/intel_quark/quark_se/Kconfig.defconfig.series

@@ -16,11 +16,15 @@ config TOOLCHAIN_VARIANT
 	default "iamcu" if X86_IAMCU
 	default "" if !X86_IAMCU
 
+if !HAS_DTS
 config PHYS_RAM_ADDR
 	default 0xA8006400
+endif
 
+if !HAS_DTS
 config PHYS_LOAD_ADDR
 	default 0x40030000 if XIP
+endif
 
 config RAM_SIZE
 	default 55
@@ -200,8 +204,10 @@ config BLUETOOTH_UART_ON_DEV_NAME
 config UART_QMSI_0
 	def_bool y
 
+if !HAS_DTS
 config UART_QMSI_0_BAUDRATE
 	default 1000000
+endif
 
 config UART_QMSI_0_HW_FC
 	def_bool y

arch/x86/soc/intel_quark/quark_se/linker.ld

@@ -13,6 +13,7 @@
 
 #include <autoconf.h>
 
+#include <generated_dts_board.h>
 /* physical address of RAM (needed for correct __ram_phys_end symbol) */
 #define PHYS_RAM_ADDR    CONFIG_PHYS_RAM_ADDR
 

dts/x86/Makefile

@@ -0,0 +1,4 @@
+ifeq ($(CONFIG_HAS_DTS),y)
+dtb-$(CONFIG_SOC_QUARK_SE_C1000)	=	arduino_101.dts_compiled
+always	:= $(dtb-y)
+endif

dts/x86/intel_curie.dtsi

@@ -0,0 +1,61 @@
+#include "skeleton.dtsi"
+#include "mem.h"
+
+/ {
+	cpus {
+		cpu@0 {
+			compatible = "intel,quark";
+		};
+
+		cpu@1 {
+			compatible = "arc";
+		};
+	};
+
+	flash0: flash@40010000 {
+		reg = <0x40010000 DT_FLASH_SIZE>;
+	};
+
+
+	sram0: memory@a8006400 {
+		reg = <0xa8006400 DT_SRAM_SIZE>;
+	};
+
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges;
+
+		rtc: rtc@b0000400 {
+			compatible = "intel,qmsi-rtc";
+			reg = <0xb0000400 0x400>;
+			clock-frequency = <32768>;
+		};
+
+		uart0: uart@b0002000 {
+			compatible = "intel,qmsi-uart";
+			reg = <0xb0002000 0x400>;
+			label = "UART_0";
+
+			status = "disabled";
+		};
+
+		uart1: uart@b0002400 {
+			compatible = "intel,qmsi-uart";
+			reg = <0xb0002400 0x400>;
+			label = "UART_1";
+
+			status = "disabled";
+		};
+
+		gpio: gpio@b000c000 {
+			compatible = "intel,qmsi-gpio";
+			reg = <0xb00c00 0x400>;
+
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+	};
+};

dts/x86/mem.h

@@ -0,0 +1,13 @@
+#ifndef __DT_BINDING_ST_MEM_H
+#define __DT_BINDING_ST_MEM_H
+
+#define __SIZE_K(x) (x * 1024)
+
+#if defined(CONFIG_SOC_QUARK_SE_C1000)
+#define DT_FLASH_SIZE		__SIZE_K(144)
+#define DT_SRAM_SIZE		__SIZE_K(55)
+#else
+#error "Flash and RAM sizes not defined for this chip"
+#endif
+
+#endif /* __DT_BINDING_ST_MEM_H */

include/arch/x86/arch.h

@@ -17,6 +17,7 @@
 #include <irq.h>
 #include <arch/x86/irq_controller.h>
 #include <kernel_arch_thread.h>
+#include <generated_dts_board.h>
 
 #ifndef _ASMLANGUAGE
 #include <arch/x86/asm_inline.h>