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dts: bindings: fix typo in (net, power-domain, pwm, qspi)

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Utilize a code spell-checking tool to scan for and correct spelling errors
in all files within the dts/bindings/net, power-domain, pwm and qspi.

Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
This commit is contained in:
Pisit Sawangvonganan 2024-01-28 20:11:16 +07:00 committed by Anas Nashif
parent 31a82699a8
commit cfa9eeb12c
4 changed files with 4 additions and 4 deletions
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2
dts/bindings/net/wireless/gpio-radio-coex.yaml
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@ -2,7 +2,7 @@
# SPDX-License-Identifier: Apache-2.0
description: |
Generic representation of Coexistance pin interface for radios. This
Generic representation of Coexistence pin interface for radios. This
interface is usually available on Wifi/Bluetooth/LTE modules to
interact with each other when sharing same antenna. This prevents
any collisions between transmissions from different modules. The grant

2
dts/bindings/power-domain/power-domain-gpio-monitor.yaml
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@ -6,7 +6,7 @@ description: |
This power domain monitors the state of a GPIO pin to detect whether a power
rail is on/off. Therefore, performing resume/suspend on power domain won't
change physical state of power rails and those action won't be triggerd on
change physical state of power rails and those action won't be triggered on
child nodes. Additionally, due to the asynchronous nature of monitoring a
pending transaction won't be interrupted by power state change.

2
dts/bindings/pwm/nxp,s32-emios-pwm.yaml
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@ -179,7 +179,7 @@ child-binding:
default: 0
enum: [0, 2, 4, 8, 16]
description: |
Select the minimim input pulse width, in filter clock cycles that can pass
Select the minimum input pulse width, in filter clock cycles that can pass
through the input filter. The filter latency - the difference in time between
the input and the response is three clock edges. Default 0 means the filter
is bypassed. The clock source for programmable input filter is eMIOS clock.

2
dts/bindings/qspi/nxp,s32-qspi.yaml
View file

@ -70,7 +70,7 @@ properties:
type: int
default: 0
description: |
Column Address Space bit width. For example, if the coulmn address is
Column Address Space bit width. For example, if the column address is
[2:0] of QSPI_SFAR/AHB address, then the column address space bit width
must be 3. If there is no column address separation in any serial flash
device connected to this controller, this value must be programmed to 0.