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intel_adsp: mem_window: support read-only flag

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Some windows might need to be set as writtable, so add a flag read-only
to DTS bindings which is set to true for all windows right now. This can
be set to false where needed.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit is contained in:
Anas Nashif 2022-09-16 10:41:45 -04:00
parent 9cd53958ce
commit d148ea1d7f
9 changed files with 23 additions and 2 deletions
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3
dts/bindings/memory-window/intel,adsp-mem-window.yaml
View file

@ -20,3 +20,6 @@ properties:
offset:
type: int
description: offset from memory base.
read-only:
type: boolean

2
dts/xtensa/intel/intel_adsp_ace15_mtpm.dtsi
View file

@ -163,6 +163,7 @@
offset = <0x4000>;
memory = <&sram0>;
initialize;
read-only;
};
mem_window1: mem_window@70208 {
compatible = "intel,adsp-mem-window";
@ -180,6 +181,7 @@
compatible = "intel,adsp-mem-window";
reg = <0x70218 0x8>;
memory = <&sram0>;
read-only;
};
tlb: tlb@17e000 {

2
dts/xtensa/intel/intel_adsp_cavs15.dtsi
View file

@ -79,6 +79,7 @@
offset = <0x6000>;
memory = <&sram0>;
initialize;
read-only;
};
mem_window1: mem_window@1588 {
compatible = "intel,adsp-mem-window";
@ -96,6 +97,7 @@
compatible = "intel,adsp-mem-window";
reg = <0x1598 0x8>;
memory = <&sram0>;
read-only;
};
core_intc: core_intc@0 {

2
dts/xtensa/intel/intel_adsp_cavs18.dtsi
View file

@ -71,6 +71,7 @@
offset = <0x4000>;
memory = <&sram0>;
initialize;
read-only;
};
mem_window1: mem_window@71a08 {
compatible = "intel,adsp-mem-window";
@ -88,6 +89,7 @@
compatible = "intel,adsp-mem-window";
reg = <0x71a18 0x8>;
memory = <&sram0>;
read-only;
};
l2lm: l2lm@71d00 {

2
dts/xtensa/intel/intel_adsp_cavs20.dtsi
View file

@ -71,6 +71,7 @@
offset = <0x4000>;
memory = <&sram0>;
initialize;
read-only;
};
mem_window1: mem_window@71a08 {
compatible = "intel,adsp-mem-window";
@ -88,6 +89,7 @@
compatible = "intel,adsp-mem-window";
reg = <0x71a18 0x8>;
memory = <&sram0>;
read-only;
};
l2lm: l2lm@71d00 {

2
dts/xtensa/intel/intel_adsp_cavs20_jsl.dtsi
View file

@ -51,6 +51,7 @@
offset = <0x4000>;
memory = <&sram0>;
initialize;
read-only;
};
mem_window1: mem_window@71a08 {
compatible = "intel,adsp-mem-window";
@ -68,6 +69,7 @@
compatible = "intel,adsp-mem-window";
reg = <0x71a18 0x8>;
memory = <&sram0>;
read-only;
};
l2lm: l2lm@71d00 {
compatible = "intel,cavs-l2lm";

2
dts/xtensa/intel/intel_adsp_cavs25.dtsi
View file

@ -91,6 +91,7 @@
offset = <0x4000>;
memory = <&sram0>;
initialize;
read-only;
};
mem_window1: mem_window@71a08 {
compatible = "intel,adsp-mem-window";
@ -108,6 +109,7 @@
compatible = "intel,adsp-mem-window";
reg = <0x71a18 0x8>;
memory = <&sram0>;
read-only;
};
sspbase: ssp_base@71c00 {

1
soc/xtensa/intel_adsp/common/include/mem_window.h
View file

@ -14,6 +14,7 @@ struct mem_win_config {
uint32_t offset;
uint32_t mem_base;
bool initialize;
bool read_only;
};
#endif

9
soc/xtensa/intel_adsp/common/mem_window.c
View file

@ -36,8 +36,12 @@ __imr int mem_win_init(const struct device *dev)
}
sys_write32(config->size | 0x7, DMWLO(config->base_addr));
sys_write32((config->mem_base | ADSP_DMWBA_READONLY | ADSP_DMWBA_ENABLE),
DMWBA(config->base_addr));
if (config->read_only) {
sys_write32((config->mem_base | ADSP_DMWBA_READONLY | ADSP_DMWBA_ENABLE),
DMWBA(config->base_addr));
} else {
sys_write32((config->mem_base | ADSP_DMWBA_ENABLE), DMWBA(config->base_addr));
}
return 0;
}
@ -47,6 +51,7 @@ __imr int mem_win_init(const struct device *dev)
.base_addr = DT_INST_REG_ADDR(inst), \
.size = WIN_SIZE(inst), \
.offset = WIN_OFFSET(inst), \
.read_only = DT_INST_PROP(inst, read_only), \
.mem_base = DT_REG_ADDR(DT_INST_PHANDLE(inst, memory)) + WIN_OFFSET(inst), \
.initialize = DT_INST_PROP(inst, initialize), \
}; \