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dts: arm64: qemu: Fix invalid PCIe interrupt-map node

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The interrupt-map was missing the priority field.
This causes a build failure when trying to use it.
The lines are split to fit into the 100 column limit.

Signed-off-by: Grant Ramsay <gramsay@enphaseenergy.com>
This commit is contained in:
Grant Ramsay 2023-08-07 15:06:40 +12:00 committed by Carles Cufí
parent 7a9cda9199
commit de44a6c0c6
2 changed files with 64 additions and 32 deletions
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48
dts/arm64/qemu/qemu-virt-a53.dtsi
View file

@ -112,25 +112,41 @@
0x3000000 0x80 0x00 0x80 0x00 0x80 0x00>;
#interrupt-cells = <0x01>;
interrupt-map-mask = <0x1800 0x00 0x00 0x07>;
interrupt-map = <0x00 0x00 0x00 1 &gic 0 0 GIC_SPI 0x03 IRQ_TYPE_EDGE
0x00 0x00 0x00 2 &gic 0 0 GIC_SPI 0x04 IRQ_TYPE_EDGE
0x00 0x00 0x00 3 &gic 0 0 GIC_SPI 0x05 IRQ_TYPE_EDGE
0x00 0x00 0x00 4 &gic 0 0 GIC_SPI 0x06 IRQ_TYPE_EDGE
interrupt-map = <0x00 0x00 0x00 1 &gic 0 0 GIC_SPI
0x03 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY
0x00 0x00 0x00 2 &gic 0 0 GIC_SPI
0x04 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY
0x00 0x00 0x00 3 &gic 0 0 GIC_SPI
0x05 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY
0x00 0x00 0x00 4 &gic 0 0 GIC_SPI
0x06 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY
0x800 0x00 0x00 1 &gic 0 0 GIC_SPI 0x04 IRQ_TYPE_EDGE
0x800 0x00 0x00 2 &gic 0 0 GIC_SPI 0x05 IRQ_TYPE_EDGE
0x800 0x00 0x00 3 &gic 0 0 GIC_SPI 0x06 IRQ_TYPE_EDGE
0x800 0x00 0x00 4 &gic 0 0 GIC_SPI 0x03 IRQ_TYPE_EDGE
0x800 0x00 0x00 1 &gic 0 0 GIC_SPI
0x04 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY
0x800 0x00 0x00 2 &gic 0 0 GIC_SPI
0x05 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY
0x800 0x00 0x00 3 &gic 0 0 GIC_SPI
0x06 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY
0x800 0x00 0x00 4 &gic 0 0 GIC_SPI
0x03 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY
0x1000 0x00 0x00 1 &gic 0 0 GIC_SPI 0x05 IRQ_TYPE_EDGE
0x1000 0x00 0x00 2 &gic 0 0 GIC_SPI 0x06 IRQ_TYPE_EDGE
0x1000 0x00 0x00 3 &gic 0 0 GIC_SPI 0x03 IRQ_TYPE_EDGE
0x1000 0x00 0x00 4 &gic 0 0 GIC_SPI 0x04 IRQ_TYPE_EDGE
0x1000 0x00 0x00 1 &gic 0 0 GIC_SPI
0x05 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY
0x1000 0x00 0x00 2 &gic 0 0 GIC_SPI
0x06 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY
0x1000 0x00 0x00 3 &gic 0 0 GIC_SPI
0x03 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY
0x1000 0x00 0x00 4 &gic 0 0 GIC_SPI
0x04 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY
0x1800 0x00 0x00 1 &gic 0 0 GIC_SPI 0x06 IRQ_TYPE_EDGE
0x1800 0x00 0x00 2 &gic 0 0 GIC_SPI 0x03 IRQ_TYPE_EDGE
0x1800 0x00 0x00 3 &gic 0 0 GIC_SPI 0x04 IRQ_TYPE_EDGE
0x1800 0x00 0x00 4 &gic 0 0 GIC_SPI 0x05 IRQ_TYPE_EDGE>;
0x1800 0x00 0x00 1 &gic 0 0 GIC_SPI
0x06 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY
0x1800 0x00 0x00 2 &gic 0 0 GIC_SPI
0x03 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY
0x1800 0x00 0x00 3 &gic 0 0 GIC_SPI
0x04 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY
0x1800 0x00 0x00 4 &gic 0 0 GIC_SPI
0x05 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;
msi-parent = <&its>;
bus-range = <0x00 0xff>;
};

48
dts/arm64/qemu/qemu-virt-arm64.dtsi
View file

@ -112,25 +112,41 @@
0x3000000 0x80 0x00 0x80 0x00 0x80 0x00>;
#interrupt-cells = <0x01>;
interrupt-map-mask = <0x1800 0x00 0x00 0x07>;
interrupt-map = <0x00 0x00 0x00 1 &gic 0 0 GIC_SPI 0x03 IRQ_TYPE_EDGE
0x00 0x00 0x00 2 &gic 0 0 GIC_SPI 0x04 IRQ_TYPE_EDGE
0x00 0x00 0x00 3 &gic 0 0 GIC_SPI 0x05 IRQ_TYPE_EDGE
0x00 0x00 0x00 4 &gic 0 0 GIC_SPI 0x06 IRQ_TYPE_EDGE
interrupt-map = <0x00 0x00 0x00 1 &gic 0 0 GIC_SPI
0x03 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY
0x00 0x00 0x00 2 &gic 0 0 GIC_SPI
0x04 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY
0x00 0x00 0x00 3 &gic 0 0 GIC_SPI
0x05 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY
0x00 0x00 0x00 4 &gic 0 0 GIC_SPI
0x06 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY
0x800 0x00 0x00 1 &gic 0 0 GIC_SPI 0x04 IRQ_TYPE_EDGE
0x800 0x00 0x00 2 &gic 0 0 GIC_SPI 0x05 IRQ_TYPE_EDGE
0x800 0x00 0x00 3 &gic 0 0 GIC_SPI 0x06 IRQ_TYPE_EDGE
0x800 0x00 0x00 4 &gic 0 0 GIC_SPI 0x03 IRQ_TYPE_EDGE
0x800 0x00 0x00 1 &gic 0 0 GIC_SPI
0x04 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY
0x800 0x00 0x00 2 &gic 0 0 GIC_SPI
0x05 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY
0x800 0x00 0x00 3 &gic 0 0 GIC_SPI
0x06 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY
0x800 0x00 0x00 4 &gic 0 0 GIC_SPI
0x03 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY
0x1000 0x00 0x00 1 &gic 0 0 GIC_SPI 0x05 IRQ_TYPE_EDGE
0x1000 0x00 0x00 2 &gic 0 0 GIC_SPI 0x06 IRQ_TYPE_EDGE
0x1000 0x00 0x00 3 &gic 0 0 GIC_SPI 0x03 IRQ_TYPE_EDGE
0x1000 0x00 0x00 4 &gic 0 0 GIC_SPI 0x04 IRQ_TYPE_EDGE
0x1000 0x00 0x00 1 &gic 0 0 GIC_SPI
0x05 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY
0x1000 0x00 0x00 2 &gic 0 0 GIC_SPI
0x06 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY
0x1000 0x00 0x00 3 &gic 0 0 GIC_SPI
0x03 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY
0x1000 0x00 0x00 4 &gic 0 0 GIC_SPI
0x04 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY
0x1800 0x00 0x00 1 &gic 0 0 GIC_SPI 0x06 IRQ_TYPE_EDGE
0x1800 0x00 0x00 2 &gic 0 0 GIC_SPI 0x03 IRQ_TYPE_EDGE
0x1800 0x00 0x00 3 &gic 0 0 GIC_SPI 0x04 IRQ_TYPE_EDGE
0x1800 0x00 0x00 4 &gic 0 0 GIC_SPI 0x05 IRQ_TYPE_EDGE>;
0x1800 0x00 0x00 1 &gic 0 0 GIC_SPI
0x06 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY
0x1800 0x00 0x00 2 &gic 0 0 GIC_SPI
0x03 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY
0x1800 0x00 0x00 3 &gic 0 0 GIC_SPI
0x04 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY
0x1800 0x00 0x00 4 &gic 0 0 GIC_SPI
0x05 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;
msi-parent = <&its>;
bus-range = <0x00 0xff>;
};