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dts/riscv/efinix: add the efinix,vexriscv-sapphire compatible string

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This commit adds the `efinix,vexriscv-sapphire` compatible string. This
helps identify the core type from the final devicetree alone.

The VexRiscv core configuration is specific to the Efinix Sapphire SoC.

Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This commit is contained in:
Filip Kokosinski 2024-01-18 10:39:43 +01:00 committed by Carles Cufí
parent 0458ac064c
commit e08a77c8fe
2 changed files with 10 additions and 1 deletions
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9
dts/bindings/cpu/efinix,vexriscv-sapphire.yaml Normal file
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@ -0,0 +1,9 @@
# Copyright (c) 2024 Antmicro <www.antmicro.com>
#
# SPDX-License-Identifier: Apache-2.0
description: VexRiscv core with the configuration as used in the Efinix Sapphire SoC
compatible: "efinix,vexriscv-sapphire"
include: riscv,cpus.yaml

2
dts/riscv/efinix/sapphire_soc.dtsi
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@ -27,7 +27,7 @@
#size-cells = <0>;
cpu@0 {
clock-frequency = <100000000>;
compatible = "riscv";
compatible = "efinix,vexriscv-sapphire", "riscv";
device_type = "cpu";
reg = <0>;
riscv,isa = "rv32ima_zicsr_zifencei";