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arch: port nocache linker code to use Cmake function

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Remove from linker.ld

Signed-off-by: Øyvind Rønningstad <oyvind.ronningstad@nordicsemi.no>
This commit is contained in:
Øyvind Rønningstad 2019-03-20 13:04:45 +01:00 committed by Anas Nashif
parent 5bebf2ae5c
commit e4024e274b
3 changed files with 25 additions and 14 deletions
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5
arch/common/CMakeLists.txt
View file

@ -20,3 +20,8 @@ zephyr_linker_sources_ifdef(CONFIG_ARCH_HAS_RAMFUNC_SUPPORT
RAM_SECTIONS
ramfunc.ld
)
zephyr_linker_sources_ifdef(CONFIG_NOCACHE_MEMORY
RAM_SECTIONS
nocache.ld
)

20
arch/common/nocache.ld Normal file
View file

@ -0,0 +1,20 @@
/*
* Copyright (c) 2019 Nordic Semiconductor ASA
* Copyright (c) 2019 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
/* Copied from linker.ld */
/* Non-cached region of RAM */
SECTION_PROLOGUE(_NOCACHE_SECTION_NAME,(NOLOAD),)
{
MPU_ALIGN(_nocache_ram_size);
_nocache_ram_start = .;
*(.nocache)
*(".nocache.*")
MPU_ALIGN(_nocache_ram_size);
_nocache_ram_end = .;
} GROUP_LINK_IN(RAMABLE_REGION)
_nocache_ram_size = _nocache_ram_end - _nocache_ram_start;

14
include/arch/arm/cortex_m/scripts/linker.ld
View file

@ -361,20 +361,6 @@ SECTIONS
#endif /* CONFIG_COVERAGE_GCOV */
#if defined(CONFIG_NOCACHE_MEMORY)
/* Non-cached region of RAM */
SECTION_PROLOGUE(_NOCACHE_SECTION_NAME,(NOLOAD),)
{
MPU_ALIGN(_nocache_ram_size);
_nocache_ram_start = .;
*(.nocache)
*(".nocache.*")
MPU_ALIGN(_nocache_ram_size);
_nocache_ram_end = .;
} GROUP_LINK_IN(RAMABLE_REGION)
_nocache_ram_size = _nocache_ram_end - _nocache_ram_start;
#endif /* CONFIG_NOCACHE_MEMORY */
/* Located in generated directory. This file is populated by the
* zephyr_linker_sources() Cmake function.
*/