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soc: arm: reneas: Add r8a779f0 support

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r8a779f0 SoC is part of the Renesas R-Car Gen4 SoC series.

This SoC has a dual core lockstep Cortex-R52 CPU.

Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
This commit is contained in:
Aymeric Aillet 2023-03-21 18:09:44 +01:00 committed by Anas Nashif
parent cfb93c1c82
commit f2061a073a
6 changed files with 77 additions and 0 deletions
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15
soc/arm/renesas_rcar/gen4/Kconfig.defconfig.r8a779f0 Normal file
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# Copyright (c) 2023 IoT.bzh
# SPDX-License-Identifier: Apache-2.0
if SOC_R8A779F0
config SOC
default "r8a779f0"
config NUM_IRQS
default 1216 #960 SPI + 256 LPI
config PINCTRL
default y
endif # SOC_R8A779F0

13
soc/arm/renesas_rcar/gen4/Kconfig.defconfig.series Normal file
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# Renesas R-Car Gen4 SoC line
# Copyright (c) 2023 IoT.bzh
# SPDX-License-Identifier: Apache-2.0
if SOC_SERIES_RCAR_GEN4
source "soc/arm/renesas_rcar/gen4/Kconfig.defconfig.r8a779*"
config SOC_SERIES
default "gen4"
endif # SOC_SERIES_RCAR_GEN4

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soc/arm/renesas_rcar/gen4/Kconfig.series Normal file
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# Copyright (c) 2023 IoT.bzh
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_RCAR_GEN4
bool "Renesas R-Car Gen4 Cortex R52"
select ARM
select CPU_CORTEX_R52
select GIC_SINGLE_SECURITY_STATE
select SOC_FAMILY_RCAR
select CLOCK_CONTROL_RCAR_CPG_MSSR if CLOCK_CONTROL
select ARM_ARCH_TIMER
help
Enable support for Renesas R-Car Gen4 SoC series

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soc/arm/renesas_rcar/gen4/Kconfig.soc Normal file
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# Copyright (c) 2023 IoT.bzh
# SPDX-License-Identifier: Apache-2.0
choice
prompt "Renesas RCar SoC Selection"
depends on SOC_SERIES_RCAR_GEN4
config SOC_R8A779F0
bool "r8a779f0"
endchoice

7
soc/arm/renesas_rcar/gen4/linker.ld Normal file
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/*
* Copyright (c) 2023 IoT.bzh
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/arch/arm/cortex_a_r/scripts/linker.ld>

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soc/arm/renesas_rcar/gen4/soc.h Normal file
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/*
* Copyright (c) 2023 IoT.bzh
*
* SPDX-License-Identifier: Apache-2.0
*
*/
#ifndef _SOC__H_
#define _SOC__H_
/* Define CMSIS configurations */
#define __CR_REV 1U
/* Do not let CMSIS to handle GIC and Timer */
#define __GIC_PRESENT 0
#define __TIM_PRESENT 0
#endif /* _SOC__H_ */