intel_adsp: ace20_lnl: add initial ace 2.0 (LNL) board definition
This commit adds definition of ACE 2.0 Lunar Lake board.board. Signed-off-by: Krzysztof Frydryk <Krzysztofx.Frydryk@intel.com> Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com> Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commit is contained in:
Jaroslaw Stelter
Carles Cufí
parent
180f1ffb5c
commit
f5728c298d
8
boards/xtensa/intel_adsp_ace20_lnl/Kconfig.board
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8
boards/xtensa/intel_adsp_ace20_lnl/Kconfig.board
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@ -0,0 +1,8 @@
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# Xtensa board configuration
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# Copyright (c) 2022 Intel Corporation
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# SPDX-License-Identifier: Apache-2.0
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config BOARD_INTEL_ADSP_ACE20_LNL
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bool "Intel ADSP ACE 2.0 Lunar Lake PCH"
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depends on SOC_SERIES_INTEL_ACE
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10
boards/xtensa/intel_adsp_ace20_lnl/Kconfig.defconfig
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boards/xtensa/intel_adsp_ace20_lnl/Kconfig.defconfig
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@ -0,0 +1,10 @@
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# Copyright (c) 2022 Intel Corporation
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#
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# SPDX-License-Identifier: Apache-2.0
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if BOARD_INTEL_ADSP_ACE20_LNL
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config BOARD
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default "intel_adsp_ace20_lnl"
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endif # BOARD_INTEL_ADSP_ACE20_LNL
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5
boards/xtensa/intel_adsp_ace20_lnl/board.cmake
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boards/xtensa/intel_adsp_ace20_lnl/board.cmake
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@ -0,0 +1,5 @@
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# SPDX-License-Identifier: Apache-2.0
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set(SUPPORTED_EMU_PLATFORMS acesim)
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board_set_rimage_target(lnl)
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18
boards/xtensa/intel_adsp_ace20_lnl/intel_adsp_ace20_lnl.dts
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boards/xtensa/intel_adsp_ace20_lnl/intel_adsp_ace20_lnl.dts
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@ -0,0 +1,18 @@
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/*
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* Copyright (c) 2022 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <intel/intel_adsp_ace20_lnl.dtsi>
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/ {
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model = "intel_adsp_ace20_lnl";
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compatible = "intel";
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chosen {
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zephyr,sram = &sram0;
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};
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};
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boards/xtensa/intel_adsp_ace20_lnl/intel_adsp_ace20_lnl.yaml
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boards/xtensa/intel_adsp_ace20_lnl/intel_adsp_ace20_lnl.yaml
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identifier: intel_adsp_ace20_lnl
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name: ACE 2.0 LNL Audio DSP
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type: mcu
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arch: xtensa
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toolchain:
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- xcc
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- xt-clang
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supported:
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- dma
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testing:
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ignore_tags:
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- net
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- bluetooth
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- mcumgr
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@ -0,0 +1,14 @@
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# SPDX-License-Identifier: Apache-2.0
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CONFIG_MAIN_STACK_SIZE=2048
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CONFIG_SOC_SERIES_INTEL_ACE=y
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CONFIG_SOC_INTEL_ACE20_LNL=y
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CONFIG_BOARD_INTEL_ADSP_ACE20_LNL=y
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CONFIG_GEN_ISR_TABLES=y
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CONFIG_GEN_IRQ_VECTOR_TABLE=n
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CONFIG_BUILD_OUTPUT_BIN=n
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CONFIG_MM_DRV=y
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CONFIG_MM_DRV_INTEL_ADSP_MTL_TLB=y
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@ -23,3 +23,6 @@ properties:
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"dma-copy-alignment":
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required: true
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dma-cells:
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- channel
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364
dts/xtensa/intel/intel_adsp_ace20_lnl.dtsi
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dts/xtensa/intel/intel_adsp_ace20_lnl.dtsi
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/*
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* Copyright (c) 2022 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <xtensa/xtensa.dtsi>
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#include <mem.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "cdns,tensilica-xtensa-lx7";
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reg = <0>;
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cpu-power-states = <&d0i3 &d3>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "cdns,tensilica-xtensa-lx7";
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reg = <1>;
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cpu-power-states = <&d0i3 &d3>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "cdns,tensilica-xtensa-lx7";
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reg = <2>;
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cpu-power-states = <&d0i3 &d3>;
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "cdns,tensilica-xtensa-lx7";
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reg = <3>;
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cpu-power-states = <&d0i3 &d3>;
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};
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};
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power-states {
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d0i3: idle {
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compatible = "zephyr,power-state";
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power-state-name = "runtime-idle";
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min-residency-us = <200>;
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exit-latency-us = <100>;
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};
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/* PM_STATE_SOFT_OFF can be entered only by calling pm_state_force.
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* The procedure is triggered by IPC from the HOST (SET_DX).
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*/
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d3: off {
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compatible = "zephyr,power-state";
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power-state-name = "soft-off";
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min-residency-us = <2147483647>;
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exit-latency-us = <0>;
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};
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};
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sram0: memory@a0020000 {
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device_type = "memory";
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compatible = "mmio-sram";
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reg = <0xa0020000 DT_SIZE_K(2816)>;
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};
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sram1: memory@a0000000 {
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device_type = "memory";
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compatible = "mmio-sram";
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reg = <0xa0000000 DT_SIZE_K(64)>;
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};
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sysclk: system-clock {
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compatible = "fixed-clock";
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clock-frequency = <38400000>;
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#clock-cells = <0>;
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};
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audioclk: audio-clock {
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compatible = "fixed-clock";
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clock-frequency = <24576000>;
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#clock-cells = <0>;
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};
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pllclk: pll-clock {
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compatible = "fixed-clock";
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clock-frequency = <96000000>;
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#clock-cells = <0>;
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};
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IMR1: memory@A1000000 {
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compatible = "intel,adsp-imr";
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reg = <0xA1000000 DT_SIZE_M(16)>;
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block-size = <0x1000>;
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zephyr,memory-region = "IMR1";
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};
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soc {
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core_intc: core_intc@0 {
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compatible = "cdns,xtensa-core-intc";
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reg = <0x00 0x400>;
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interrupt-controller;
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#interrupt-cells = <3>;
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};
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adsp_host_ipc: ace_host_ipc@73000 {
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compatible = "intel,adsp-host-ipc";
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status = "okay";
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reg = <0x73000 0x30>;
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interrupts = <0 0 0>;
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interrupt-parent = <&ace_intc>;
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};
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adsp_idc: ace_idc@70400 {
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compatible = "intel,adsp-idc";
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reg = <0x70400 0x0400>;
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interrupts = <24 0 0>;
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interrupt-parent = <&ace_intc>;
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};
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/* This is actually an array of per-core designware
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* controllers, but the special setup and extra
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* masking layer makes it easier for LNL to handle
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* this internally.
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*/
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ace_intc: ace_intc@7ac00 {
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compatible = "intel,ace-intc";
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reg = <0x7ac00 0xc00>;
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupts = <4 0 0>;
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num-irqs = <28>;
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interrupt-parent = <&core_intc>;
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};
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ace_timestamp: ace_timestamp@72040 {
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compatible = "intel,ace-timestamp";
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reg = <0x72040 0x0032>;
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};
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ace_art_counter: ace_art_counter@72058 {
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compatible = "intel,ace-art-counter";
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reg = <0x72058 0x0064>;
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};
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ace_rtc_counter: ace_rtc_counter@72008 {
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compatible = "intel,ace-rtc-counter";
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reg = <0x72008 0x0064>;
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};
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lps: lps@71ac0 {
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compatible = "intel,adsp-lps";
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reg = <0x00071ac0 0x100>;
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};
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sspbase: ssp_base@28000 {
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compatible = "intel,ssp-sspbase";
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reg = <0x28000 0x1000>;
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};
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win: win@70200 {
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compatible = "intel,cavs-win";
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reg = <0x70200 0x30>;
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};
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tlb: tlb@17e000 {
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compatible = "intel,adsp-tlb";
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reg = <0x17e000 0x1000>;
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paddr-size = <12>;
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exec-bit-idx = <14>;
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write-bit-idx= <15>;
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};
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hda_host_out: dma@72800 {
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compatible = "intel,adsp-hda-host-out";
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#dma-cells = <1>;
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reg = <0x00072800 0x40>;
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dma-channels = <9>;
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dma-buf-alignment = <128>;
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status = "okay";
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};
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hda_host_in: dma@72c00 {
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compatible = "intel,adsp-hda-host-in";
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#dma-cells = <1>;
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reg = <0x00072c00 0x40>;
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dma-channels = <11>;
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dma-buf-alignment = <128>;
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status = "okay";
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};
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hda_link_out: dma@79400 {
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compatible = "intel,adsp-hda-link-out";
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#dma-cells = <1>;
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reg = <0x00079400 0x40>;
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dma-channels = <9>;
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dma-buf-alignment = <128>;
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status = "okay";
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};
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hda_link_in: dma@79800 {
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compatible = "intel,adsp-hda-link-in";
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#dma-cells = <1>;
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reg = <0x00079800 0x40>;
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dma-channels = <11>;
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dma-buf-alignment = <128>;
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status = "okay";
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};
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dmic0: dai-dmic@10000 {
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compatible = "intel,dai-dmic";
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reg = <0x10100 0x8000>;
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shim = <0xcc0 0x10>;
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interrupts = <0x08 0 0>;
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interrupt-parent = <&ace_intc>;
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};
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dmic1: dai-dmic@10001 {
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compatible = "intel,dai-dmic";
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reg = <0x10100 0x8000>;
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shim = <0xcc0 0x10>;
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interrupts = <0x08 0 0>;
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interrupt-parent = <&ace_intc>;
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};
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ssp0:ssp@28100 {
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compatible = "intel,ssp-dai";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x00028100 0x1000
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0x00079C00 0x200>;
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interrupts = <0x00 0 0>;
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interrupt-parent = <&ace_intc>;
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dmas = <&hda_link_out 1
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&hda_link_in 1>;
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dma-names = "tx", "rx";
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power-domain = <&io0_domain>;
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status = "okay";
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};
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ssp1:ssp@29100 {
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compatible = "intel,ssp-dai";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x00029100 0x1000
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0x00079C00 0x200>;
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interrupts = <0x01 0 0>;
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interrupt-parent = <&ace_intc>;
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dmas = <&hda_link_out 2
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&hda_link_in 2>;
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dma-names = "tx", "rx";
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power-domain = <&io0_domain>;
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status = "okay";
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};
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ssp2:ssp@2a100 {
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compatible = "intel,ssp-dai";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0002a100 0x1000
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0x00079C00 0x200>;
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interrupts = <0x02 0 0>;
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interrupt-parent = <&ace_intc>;
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dmas = <&hda_link_out 3
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&hda_link_in 3>;
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dma-names = "tx", "rx";
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power-domain = <&io0_domain>;
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status = "okay";
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};
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ssp3:ssp@2b100 {
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compatible = "intel,ssp-dai";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0002b100 0x1000
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0x00079C00 0x200>;
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interrupts = <0x03 0 0>;
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interrupt-parent = <&ace_intc>;
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dmas = <&hda_link_out 4
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&hda_link_in 4>;
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dma-names = "tx", "rx";
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power-domain = <&io0_domain>;
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status = "okay";
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};
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ssp4:ssp@2c100 {
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compatible = "intel,ssp-dai";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0002c100 0x1000
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0x00079C00 0x200>;
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interrupts = <0x04 0 0>;
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interrupt-parent = <&ace_intc>;
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dmas = <&hda_link_out 5
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&hda_link_in 5>;
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dma-names = "tx", "rx";
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power-domain = <&io0_domain>;
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status = "okay";
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};
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ssp5:ssp@2d100 {
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compatible = "intel,ssp-dai";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0002d100 0x1000
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0x00079C00 0x200>;
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interrupts = <0x04 0 0>;
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interrupt-parent = <&ace_intc>;
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dmas = <&hda_link_out 6
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&hda_link_in 6>;
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dma-names = "tx", "rx";
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power-domain = <&io0_domain>;
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status = "okay";
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};
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hub_ulp_domain: hub_ulp_domain {
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compatible = "intel,adsp-power-domain";
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lps = <&lps>;
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bit-position = <15>;
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};
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hub_hp_domain: hub_hpp_domain {
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compatible = "intel,adsp-power-domain";
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lps = <&lps>;
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bit-position = <6>;
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};
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io0_domain: io0_domain {
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compatible = "intel,adsp-power-domain";
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lps = <&lps>;
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bit-position = <8>;
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};
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io1_domain: io1_domain {
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compatible = "intel,adsp-power-domain";
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lps = <&lps>;
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bit-position = <9>;
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};
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io2_domain: io2_domain {
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compatible = "intel,adsp-power-domain";
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lps = <&lps>;
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bit-position = <10>;
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};
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io3_domain: io3_domain {
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compatible = "intel,adsp-power-domain";
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lps = <&lps>;
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bit-position = <11>;
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};
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hst_domain: hst_domain {
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compatible = "intel,adsp-power-domain";
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lps = <&lps>;
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bit-position = <4>;
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};
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ml0_domain: ml0_domain {
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compatible = "intel,adsp-power-domain";
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lps = <&lps>;
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bit-position = <12>;
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};
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ml1_domain: ml1_domain {
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compatible = "intel,adsp-power-domain";
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lps = <&lps>;
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bit-position = <13>;
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};
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};
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};
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