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arch: riscv: drop RISCV_HAS_CPU_IDLE

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Because it was exclusively used by the "common" RISC-V privileged code
to build CPU idle routines that are now handled by arch level code.
Also, all platforms defaulted to "y", making it pointless in practice.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
This commit is contained in:
Gerard Marull-Paretas 2024-01-10 13:05:28 +01:00 committed by Carles Cufí
parent 7631e0ddfa
commit f885763b50
19 changed files with 3 additions and 62 deletions
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5
arch/riscv/Kconfig
View file

@ -174,11 +174,6 @@ config RISCV_GENERIC_TOOLCHAIN
Allow SOCs that have custom extended riscv ISA to still
compile with generic riscv32 toolchain.
config RISCV_HAS_CPU_IDLE
bool "Does SOC has CPU IDLE instruction"
help
Does SOC has CPU IDLE instruction
config GEN_ISR_TABLES
default y

3
soc/riscv/andes_v5/ae350/Kconfig.defconfig.series
View file

@ -24,9 +24,6 @@ config RISCV_GENERIC_TOOLCHAIN
config RISCV_SOC_INTERRUPT_INIT
default y
config RISCV_HAS_CPU_IDLE
default y
config RISCV_HAS_PLIC
default y

4
soc/riscv/efinix_sapphire/Kconfig.defconfig
View file

@ -9,10 +9,6 @@ config SOC
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 100000000
config RISCV_HAS_CPU_IDLE
bool
default y
config RISCV_SOC_INTERRUPT_INIT
bool
default y

3
soc/riscv/gd_gd32/gd32vf103/Kconfig.defconfig.gd32vf103
View file

@ -20,9 +20,6 @@ config RISCV_SOC_MCAUSE_EXCEPTION_MASK
config RISCV_SOC_INTERRUPT_INIT
default y
config RISCV_HAS_CPU_IDLE
default y
config RISCV_GP
default y

3
soc/riscv/intel_niosv/niosv/Kconfig.defconfig.series
View file

@ -12,9 +12,6 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC
config NUM_IRQS # Platform interrupts IRQs index start from index 16
default 32
config RISCV_HAS_CPU_IDLE
default y
config RISCV_GP
default y

3
soc/riscv/ite_ec/it8xxx2/Kconfig.defconfig.series
View file

@ -22,9 +22,6 @@ config UART_NS16550_WA_ISR_REENABLE_INTERRUPT
default y
depends on UART_NS16550
config RISCV_HAS_CPU_IDLE
default y
config FLASH_INIT_PRIORITY
default 0

3
soc/riscv/litex_vexriscv/Kconfig.defconfig
View file

@ -9,9 +9,6 @@ config SOC
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 100000000
config RISCV_HAS_CPU_IDLE
bool
config RISCV_HAS_PLIC
bool

3
soc/riscv/microchip_miv/miv/Kconfig.defconfig.series
View file

@ -11,9 +11,6 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC
config RISCV_SOC_INTERRUPT_INIT
default y
config RISCV_HAS_CPU_IDLE
default y
config RISCV_HAS_PLIC
default y

3
soc/riscv/microchip_miv/polarfire/Kconfig.defconfig.series
View file

@ -14,9 +14,6 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC
config RISCV_SOC_INTERRUPT_INIT
default y
config RISCV_HAS_CPU_IDLE
default y
config RISCV_HAS_PLIC
default y

3
soc/riscv/neorv32/Kconfig.defconfig
View file

@ -12,9 +12,6 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC
config NUM_IRQS
default 32
config RISCV_HAS_CPU_IDLE
default y
config RISCV_GP
default y

3
soc/riscv/opentitan/Kconfig.defconfig
View file

@ -12,9 +12,6 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC
config RISCV_SOC_INTERRUPT_INIT
default y
config RISCV_HAS_CPU_IDLE
default y
config RISCV_HAS_PLIC
default y

3
soc/riscv/renode_virt/Kconfig.defconfig
View file

@ -12,9 +12,6 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC
config RISCV_SOC_INTERRUPT_INIT
default y
config RISCV_HAS_CPU_IDLE
default y
config RISCV_HAS_PLIC
default y

3
soc/riscv/sifive_freedom/e300/Kconfig.defconfig.series
View file

@ -12,9 +12,6 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC
config RISCV_SOC_INTERRUPT_INIT
default y
config RISCV_HAS_CPU_IDLE
default y
config RISCV_HAS_PLIC
default y

3
soc/riscv/sifive_freedom/u500/Kconfig.defconfig.series
View file

@ -12,9 +12,6 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC
config RISCV_SOC_INTERRUPT_INIT
default y
config RISCV_HAS_CPU_IDLE
default y
config RISCV_HAS_PLIC
default y

3
soc/riscv/sifive_freedom/u700/Kconfig.defconfig.series
View file

@ -12,9 +12,6 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC
config RISCV_SOC_INTERRUPT_INIT
default y
config RISCV_HAS_CPU_IDLE
default y
config RISCV_HAS_PLIC
default y

3
soc/riscv/starfive_jh71xx/jh71xx/Kconfig.defconfig.series
View file

@ -12,9 +12,6 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC
config RISCV_SOC_INTERRUPT_INIT
default y
config RISCV_HAS_CPU_IDLE
default y
config RISCV_HAS_PLIC
default y

4
soc/riscv/telink_tlsr/tlsr951x/Kconfig.defconfig.series
View file

@ -15,10 +15,6 @@ config RISCV_SOC_INTERRUPT_INIT
bool
default y
config RISCV_HAS_CPU_IDLE
bool
default y
config RISCV_HAS_PLIC
bool
default y

3
soc/riscv/virt/Kconfig.defconfig
View file

@ -12,9 +12,6 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC
config RISCV_SOC_INTERRUPT_INIT
default y
config RISCV_HAS_CPU_IDLE
default y
config RISCV_HAS_PLIC
default y

7
tests/kernel/context/src/main.c
View file

@ -72,11 +72,10 @@ extern const int32_t z_sys_timer_irq_for_test;
#endif
/* Cortex-M1, Nios II, and RISCV without CONFIG_RISCV_HAS_CPU_IDLE
* do have a power saving instruction, so k_cpu_idle() returns immediately
/* Cortex-M1 and Nios II do have a power saving instruction, so k_cpu_idle()
* returns immediately
*/
#if !defined(CONFIG_CPU_CORTEX_M1) && !defined(CONFIG_NIOS2) && \
(!defined(CONFIG_RISCV) || defined(CONFIG_RISCV_HAS_CPU_IDLE))
#if !defined(CONFIG_CPU_CORTEX_M1) && !defined(CONFIG_NIOS2)
#define HAS_POWERSAVE_INSTRUCTION
#endif