drivers: timer: xlnx_psttc_timer: Implement tickless support
This commit reworks the Xilinx TTC timer driver to use the "match" mode instead of the "interval" mode which counts up to the specified value and resets to zero. Using the "match" mode ensures that the timer keeps counting even after an interrupt is triggered, and facilitates the tickless mode support implementation. This also allows `z_timer_cycle_get_32` to return the correct cycle count when interrupt is locked; thereby, fixing the k_busy_wait hang issue. Note that the TTC "match" mode emulation (and tickless timer operation) is only stable when the QEMU icount mode is enabled. Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This commit is contained in:
Stephanos Ioannidis
Anas Nashif
parent
dd75bccaca
commit
fc941d583e
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@ -212,7 +212,7 @@
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/drivers/timer/altera_avalon_timer_hal.c @wentongwu
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/drivers/timer/riscv_machine_timer.c @nategraff-sifive @kgugala @pgielda
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/drivers/timer/litex_timer.c @mateusz-holenko @kgugala @pgielda
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/drivers/timer/xlnx_psttc_timer.c @wjliang
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/drivers/timer/xlnx_psttc_timer* @wjliang @stephanosio
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/drivers/timer/cc13x2_cc26x2_rtc_timer.c @vanti
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/drivers/usb/ @jfischer-phytec-iot @finikorg
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/drivers/usb/device/usb_dc_stm32.c @ydamigos @loicpoulain
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@ -28,5 +28,5 @@
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&ttc0 {
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status = "okay";
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clock-frequency = <100000000>;
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clock-frequency = <12000000>;
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};
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@ -239,6 +239,7 @@ config XLNX_PSTTC_TIMER
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bool "Xilinx PS ttc timer support"
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default y
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depends on SOC_XILINX_ZYNQMP
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select TICKLESS_CAPABLE
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help
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This module implements a kernel device driver for the Xilinx ZynqMP
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platform provides the standard "system clock driver" interfaces.
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@ -1,187 +1,195 @@
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/*
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* Copyright (c) 2020 Stephanos Ioannidis <root@stephanos.io>
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* Copyright (c) 2018 Xilinx, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <kernel.h>
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#include <soc.h>
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#include <drivers/timer/system_timer.h>
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#include "xlnx_psttc_timer_priv.h"
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#define TIMER_INDEX CONFIG_XLNX_PSTTC_TIMER_INDEX
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#define TIMER_DT(v) UTIL_CAT(UTIL_CAT(DT_INST_, TIMER_INDEX), _##v)
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#define TIMER_IRQ TIMER_DT(XLNX_TTCPS_IRQ_0)
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#define TIMER_BASE_ADDR TIMER_DT(XLNX_TTCPS_BASE_ADDRESS)
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#define TIMER_CLOCK_FREQUECY TIMER_DT(XLNX_TTCPS_CLOCK_FREQUENCY)
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#define TICKS_PER_SEC CONFIG_SYS_CLOCK_TICKS_PER_SEC
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#define CYCLES_PER_SEC TIMER_CLOCK_FREQUECY
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#define CYCLES_PER_TICK (CYCLES_PER_SEC / TICKS_PER_SEC)
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/*
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* CYCLES_NEXT_MIN must be large enough to ensure that the timer does not miss
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* interrupts. This value was conservatively set using the trial and error
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* method, and there is room for improvement.
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*/
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#define CYCLES_NEXT_MIN (10000)
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#define CYCLES_NEXT_MAX (XTTC_MAX_INTERVAL_COUNT)
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BUILD_ASSERT_MSG(TIMER_DT(XLNX_TTCPS_CLOCK_FREQUENCY) ==
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CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC,
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"Configured system timer frequency does not match the TTC "
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"clock frequency in the device tree");
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BUILD_ASSERT_MSG(CYCLES_PER_SEC >= TICKS_PER_SEC,
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"Timer clock frequency must be greater than the system tick "
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"frequency");
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BUILD_ASSERT_MSG((CYCLES_PER_SEC % TICKS_PER_SEC) == 0,
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"Timer clock frequency is not divisible by the system tick "
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"frequency");
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#ifdef CONFIG_TICKLESS_KERNEL
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#warning "Tickless mode is not supported"
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static u32_t last_cycles;
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#endif
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#define TIMER_FREQ CONFIG_SYS_CLOCK_TICKS_PER_SEC
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#if (CONFIG_XLNX_PSTTC_TIMER_INDEX == 0)
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#define TIMER_INPUT_CLKHZ DT_INST_0_CDNS_TTC_CLOCK_FREQUENCY
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#define TIMER_IRQ DT_INST_0_CDNS_TTC_IRQ_0
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#define TIMER_BASEADDR DT_INST_0_CDNS_TTC_BASE_ADDRESS
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#else
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#error ("No timer is specified")
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#endif
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#define XTTCPS_CLK_CNTRL_OFFSET 0x00000000U /**< Clock Control Register */
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#define XTTCPS_CNT_CNTRL_OFFSET 0x0000000CU /**< Counter Control Register*/
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#define XTTCPS_COUNT_VALUE_OFFSET 0x00000018U /**< Current Counter Value */
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#define XTTCPS_INTERVAL_VAL_OFFSET 0x00000024U /**< Interval Count Value */
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#define XTTCPS_MATCH_0_OFFSET 0x00000030U /**< Match 1 value */
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#define XTTCPS_MATCH_1_OFFSET 0x0000003CU /**< Match 2 value */
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#define XTTCPS_MATCH_2_OFFSET 0x00000048U /**< Match 3 value */
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#define XTTCPS_ISR_OFFSET 0x00000054U /**< Interrupt Status Register */
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#define XTTCPS_IER_OFFSET 0x00000060U /**< Interrupt Enable Register */
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/* Clock Control Register definitions */
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#define XTTCPS_CLK_CNTRL_PS_EN_MASK 0x00000001U /**< Prescale enable */
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#define XTTCPS_CLK_CNTRL_PS_VAL_MASK 0x0000001EU /**< Prescale value */
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#define XTTCPS_CLK_CNTRL_PS_VAL_SHIFT 1U /**< Prescale shift */
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#define XTTCPS_CLK_CNTRL_PS_DISABLE 16U /**< Prescale disable */
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#define XTTCPS_CLK_CNTRL_SRC_MASK 0x00000020U /**< Clock source */
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#define XTTCPS_CLK_CNTRL_EXT_EDGE_MASK 0x00000040U /**< External Clock edge */
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/* Counter Control Register definitions */
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#define XTTCPS_CNT_CNTRL_DIS_MASK 0x00000001U /**< Disable the counter */
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#define XTTCPS_CNT_CNTRL_INT_MASK 0x00000002U /**< Interval mode */
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#define XTTCPS_CNT_CNTRL_DECR_MASK 0x00000004U /**< Decrement mode */
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#define XTTCPS_CNT_CNTRL_MATCH_MASK 0x00000008U /**< Match mode */
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#define XTTCPS_CNT_CNTRL_RST_MASK 0x00000010U /**< Reset counter */
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#define XTTCPS_CNT_CNTRL_EN_WAVE_MASK 0x00000020U /**< Enable waveform */
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#define XTTCPS_CNT_CNTRL_POL_WAVE_MASK 0x00000040U /**< Waveform polarity */
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#define XTTCPS_CNT_CNTRL_RESET_VALUE 0x00000021U /**< Reset value */
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/* Interrupt register masks */
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#define XTTCPS_IXR_INTERVAL_MASK 0x00000001U /**< Interval Interrupt */
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#define XTTCPS_IXR_MATCH_0_MASK 0x00000002U /**< Match 1 Interrupt */
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#define XTTCPS_IXR_MATCH_1_MASK 0x00000004U /**< Match 2 Interrupt */
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#define XTTCPS_IXR_MATCH_2_MASK 0x00000008U /**< Match 3 Interrupt */
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#define XTTCPS_IXR_CNT_OVR_MASK 0x00000010U /**< Counter Overflow */
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#define XTTCPS_IXR_ALL_MASK 0x0000001FU /**< All valid Interrupts */
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#define XTTC_MAX_INTERVAL_COUNT 0xFFFFFFFFU /**< Maximum value of interval counter */
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static u32_t accumulated_cycles;
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static s32_t _sys_idle_elapsed_ticks = 1;
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static int xttc_calculate_interval(u32_t *interval, u8_t *prescaler)
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static u32_t read_count(void)
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{
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u32_t tmpinterval = 0;
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u8_t tmpprescaler = 0;
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unsigned int tmpval;
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tmpval = (u32_t)(TIMER_INPUT_CLKHZ / TIMER_FREQ);
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if (tmpval < (u32_t)65536U) {
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/* no prescaler is required */
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tmpinterval = tmpval;
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tmpprescaler = 0;
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} else {
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for (tmpprescaler = 1U; tmpprescaler < 16; tmpprescaler++) {
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tmpval = (u32_t)(TIMER_INPUT_CLKHZ /
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(TIMER_FREQ * (1U << tmpprescaler)));
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if (tmpval < (u32_t)65536U) {
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tmpinterval = tmpval;
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break;
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}
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}
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}
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if (tmpinterval != 0) {
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*interval = tmpinterval;
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*prescaler = tmpprescaler;
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return 0;
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}
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/* TBD: Is there a way to adjust the sys clock parameters such as
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* ticks per sec if it failed to configure the timer as specified
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*/
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return -EINVAL;
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/* Read current counter value */
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return sys_read32(TIMER_BASE_ADDR + XTTCPS_COUNT_VALUE_OFFSET);
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}
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/**
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* @brief System timer tick handler
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*
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* This routine handles the system clock tick interrupt. A TICK_EVENT event
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* is pushed onto the kernel stack.
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*
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* The symbol for this routine is either _timer_int_handler.
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*
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* @return N/A
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*/
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void _timer_int_handler(void *unused)
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static void update_match(u32_t cycles, u32_t match)
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{
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ARG_UNUSED(unused);
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u32_t delta = match - cycles;
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u32_t regval;
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/* Ensure that the match value meets the minimum timing requirements */
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if (delta < CYCLES_NEXT_MIN) {
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match += CYCLES_NEXT_MIN - delta;
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}
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regval = sys_read32(TIMER_BASEADDR + XTTCPS_ISR_OFFSET);
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accumulated_cycles += k_ticks_to_cyc_floor32(1);
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z_clock_announce(_sys_idle_elapsed_ticks);
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/* Write counter match value for interrupt generation */
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sys_write32(match, TIMER_BASE_ADDR + XTTCPS_MATCH_0_OFFSET);
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}
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static void ttc_isr(void *arg)
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{
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u32_t cycles;
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u32_t ticks;
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ARG_UNUSED(arg);
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/* Acknowledge interrupt */
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sys_read32(TIMER_BASE_ADDR + XTTCPS_ISR_OFFSET);
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/* Read counter value */
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cycles = read_count();
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#ifdef CONFIG_TICKLESS_KERNEL
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/* Calculate the number of ticks since last announcement */
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ticks = (cycles - last_cycles) / CYCLES_PER_TICK;
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/* Update last cycles count */
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last_cycles = cycles;
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#else
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/* Update counter match value for the next interrupt */
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update_match(cycles, cycles + CYCLES_PER_TICK);
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/* Advance tick count by 1 */
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ticks = 1;
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#endif
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/* Announce to the kernel*/
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z_clock_announce(ticks);
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}
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int z_clock_driver_init(struct device *device)
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{
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int ret;
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u32_t interval;
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u8_t prescaler;
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u32_t regval;
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u32_t reg_val;
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/* Stop timer */
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sys_write32(XTTCPS_CNT_CNTRL_DIS_MASK,
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TIMER_BASEADDR + XTTCPS_CNT_CNTRL_OFFSET);
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TIMER_BASE_ADDR + XTTCPS_CNT_CNTRL_OFFSET);
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/* Calculate prescaler */
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ret = xttc_calculate_interval(&interval, &prescaler);
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if (ret < 0) {
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printk("Failed to calculate prescaler.\n");
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return ret;
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}
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#ifdef CONFIG_TICKLESS_KERNEL
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/* Initialise internal states */
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last_cycles = 0;
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#endif
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/* Reset registers */
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/* Initialise timer registers */
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sys_write32(XTTCPS_CNT_CNTRL_RESET_VALUE,
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TIMER_BASEADDR + XTTCPS_CNT_CNTRL_OFFSET);
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sys_write32(0, TIMER_BASEADDR + XTTCPS_CLK_CNTRL_OFFSET);
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sys_write32(0, TIMER_BASEADDR + XTTCPS_INTERVAL_VAL_OFFSET);
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sys_write32(0, TIMER_BASEADDR + XTTCPS_MATCH_0_OFFSET);
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sys_write32(0, TIMER_BASEADDR + XTTCPS_MATCH_1_OFFSET);
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sys_write32(0, TIMER_BASEADDR + XTTCPS_MATCH_2_OFFSET);
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sys_write32(0, TIMER_BASEADDR + XTTCPS_IER_OFFSET);
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sys_write32(XTTCPS_IXR_ALL_MASK, TIMER_BASEADDR + XTTCPS_ISR_OFFSET);
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TIMER_BASE_ADDR + XTTCPS_CNT_CNTRL_OFFSET);
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sys_write32(0, TIMER_BASE_ADDR + XTTCPS_CLK_CNTRL_OFFSET);
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sys_write32(0, TIMER_BASE_ADDR + XTTCPS_INTERVAL_VAL_OFFSET);
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sys_write32(0, TIMER_BASE_ADDR + XTTCPS_MATCH_0_OFFSET);
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sys_write32(0, TIMER_BASE_ADDR + XTTCPS_MATCH_1_OFFSET);
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sys_write32(0, TIMER_BASE_ADDR + XTTCPS_MATCH_2_OFFSET);
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sys_write32(0, TIMER_BASE_ADDR + XTTCPS_IER_OFFSET);
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sys_write32(XTTCPS_IXR_ALL_MASK, TIMER_BASE_ADDR + XTTCPS_ISR_OFFSET);
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/* Reset counter value */
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regval = sys_read32(TIMER_BASEADDR + XTTCPS_CNT_CNTRL_OFFSET);
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regval |= XTTCPS_CNT_CNTRL_RST_MASK;
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sys_write32(regval, TIMER_BASEADDR + XTTCPS_CNT_CNTRL_OFFSET);
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reg_val = sys_read32(TIMER_BASE_ADDR + XTTCPS_CNT_CNTRL_OFFSET);
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reg_val |= XTTCPS_CNT_CNTRL_RST_MASK;
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sys_write32(reg_val, TIMER_BASE_ADDR + XTTCPS_CNT_CNTRL_OFFSET);
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/* Set options */
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regval = sys_read32(TIMER_BASEADDR + XTTCPS_CNT_CNTRL_OFFSET);
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regval |= XTTCPS_CNT_CNTRL_INT_MASK;
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sys_write32(regval, TIMER_BASEADDR + XTTCPS_CNT_CNTRL_OFFSET);
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/* Set match mode */
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reg_val = sys_read32(TIMER_BASE_ADDR + XTTCPS_CNT_CNTRL_OFFSET);
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reg_val |= XTTCPS_CNT_CNTRL_MATCH_MASK;
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sys_write32(reg_val, TIMER_BASE_ADDR + XTTCPS_CNT_CNTRL_OFFSET);
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/* Set interval and prescaller */
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sys_write32(interval, TIMER_BASEADDR + XTTCPS_INTERVAL_VAL_OFFSET);
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regval = (u32_t)((prescaler & 0xFU) << 1);
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sys_write32(regval, TIMER_BASEADDR + XTTCPS_CLK_CNTRL_OFFSET);
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/* Set initial timeout */
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reg_val = IS_ENABLED(CONFIG_TICKLESS_KERNEL) ?
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CYCLES_NEXT_MAX : CYCLES_PER_TICK;
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sys_write32(reg_val, TIMER_BASE_ADDR + XTTCPS_MATCH_0_OFFSET);
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/* Connect timer interrupt */
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IRQ_CONNECT(TIMER_IRQ, 0, ttc_isr, 0, 0);
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irq_enable(TIMER_IRQ);
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/* Enable timer interrupt */
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IRQ_CONNECT(TIMER_IRQ, 0, _timer_int_handler, 0, 0);
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irq_enable(TIMER_IRQ);
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regval = sys_read32(TIMER_BASEADDR + XTTCPS_IER_OFFSET);
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regval |= XTTCPS_IXR_INTERVAL_MASK;
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sys_write32(regval, TIMER_BASEADDR + XTTCPS_IER_OFFSET);
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reg_val = sys_read32(TIMER_BASE_ADDR + XTTCPS_IER_OFFSET);
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reg_val |= XTTCPS_IXR_MATCH_0_MASK;
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sys_write32(reg_val, TIMER_BASE_ADDR + XTTCPS_IER_OFFSET);
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/* Start timer */
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regval = sys_read32(TIMER_BASEADDR + XTTCPS_CNT_CNTRL_OFFSET);
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regval &= (~XTTCPS_CNT_CNTRL_DIS_MASK);
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sys_write32(regval, TIMER_BASEADDR + XTTCPS_CNT_CNTRL_OFFSET);
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reg_val = sys_read32(TIMER_BASE_ADDR + XTTCPS_CNT_CNTRL_OFFSET);
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reg_val &= (~XTTCPS_CNT_CNTRL_DIS_MASK);
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sys_write32(reg_val, TIMER_BASE_ADDR + XTTCPS_CNT_CNTRL_OFFSET);
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return 0;
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}
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void z_clock_set_timeout(s32_t ticks, bool idle)
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{
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#ifdef CONFIG_TICKLESS_KERNEL
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u32_t cycles;
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u32_t next_cycles;
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/* Read counter value */
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cycles = read_count();
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/* Calculate timeout counter value */
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if (ticks == K_FOREVER) {
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next_cycles = cycles + CYCLES_NEXT_MAX;
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} else {
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next_cycles = cycles + ((u32_t)ticks * CYCLES_PER_TICK);
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}
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/* Set match value for the next interrupt */
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update_match(cycles, next_cycles);
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#endif
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}
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u32_t z_clock_elapsed(void)
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{
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#ifdef CONFIG_TICKLESS_KERNEL
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u32_t cycles;
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/* Read counter value */
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cycles = read_count();
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/* Return the number of ticks since last announcement */
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return (cycles - last_cycles) / CYCLES_PER_TICK;
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#else
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/* Always return 0 for tickful operation */
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return 0;
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#endif
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}
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u32_t z_timer_cycle_get_32(void)
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{
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return accumulated_cycles;
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/* Return the current counter value */
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return read_count();
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}
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101
drivers/timer/xlnx_psttc_timer_priv.h
Normal file
101
drivers/timer/xlnx_psttc_timer_priv.h
Normal file
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@ -0,0 +1,101 @@
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/*
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* Copyright (c) 2019 Stephanos Ioannidis <root@stephanos.io>
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* Copyright (c) 2018 Xilinx, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_DRIVERS_TIMER_XLNX_PSTTC_TIMER_PRIV_H_
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#define ZEPHYR_DRIVERS_TIMER_XLNX_PSTTC_TIMER_PRIV_H_
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/*
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* Refer to the "Zynq UltraScale+ Device Technical Reference Manual" document
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* from Xilinx for more information on this peripheral.
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*/
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/*
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* Triple-timer Counter (TTC) Register Offsets
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*/
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/* Clock Control Register */
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#define XTTCPS_CLK_CNTRL_OFFSET 0x00000000U
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/* Counter Control Register*/
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#define XTTCPS_CNT_CNTRL_OFFSET 0x0000000CU
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/* Current Counter Value */
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#define XTTCPS_COUNT_VALUE_OFFSET 0x00000018U
|
||||
/* Interval Count Value */
|
||||
#define XTTCPS_INTERVAL_VAL_OFFSET 0x00000024U
|
||||
/* Match 1 value */
|
||||
#define XTTCPS_MATCH_0_OFFSET 0x00000030U
|
||||
/* Match 2 value */
|
||||
#define XTTCPS_MATCH_1_OFFSET 0x0000003CU
|
||||
/* Match 3 value */
|
||||
#define XTTCPS_MATCH_2_OFFSET 0x00000048U
|
||||
/* Interrupt Status Register */
|
||||
#define XTTCPS_ISR_OFFSET 0x00000054U
|
||||
/* Interrupt Enable Register */
|
||||
#define XTTCPS_IER_OFFSET 0x00000060U
|
||||
|
||||
/*
|
||||
* Clock Control Register Definitions
|
||||
*/
|
||||
|
||||
/* Prescale enable */
|
||||
#define XTTCPS_CLK_CNTRL_PS_EN_MASK 0x00000001U
|
||||
/* Prescale value */
|
||||
#define XTTCPS_CLK_CNTRL_PS_VAL_MASK 0x0000001EU
|
||||
/* Prescale shift */
|
||||
#define XTTCPS_CLK_CNTRL_PS_VAL_SHIFT 1U
|
||||
/* Prescale disable */
|
||||
#define XTTCPS_CLK_CNTRL_PS_DISABLE 16U
|
||||
/* Clock source */
|
||||
#define XTTCPS_CLK_CNTRL_SRC_MASK 0x00000020U
|
||||
/* External Clock edge */
|
||||
#define XTTCPS_CLK_CNTRL_EXT_EDGE_MASK 0x00000040U
|
||||
|
||||
/*
|
||||
* Counter Control Register Definitions
|
||||
*/
|
||||
|
||||
/* Disable the counter */
|
||||
#define XTTCPS_CNT_CNTRL_DIS_MASK 0x00000001U
|
||||
/* Interval mode */
|
||||
#define XTTCPS_CNT_CNTRL_INT_MASK 0x00000002U
|
||||
/* Decrement mode */
|
||||
#define XTTCPS_CNT_CNTRL_DECR_MASK 0x00000004U
|
||||
/* Match mode */
|
||||
#define XTTCPS_CNT_CNTRL_MATCH_MASK 0x00000008U
|
||||
/* Reset counter */
|
||||
#define XTTCPS_CNT_CNTRL_RST_MASK 0x00000010U
|
||||
/* Enable waveform */
|
||||
#define XTTCPS_CNT_CNTRL_EN_WAVE_MASK 0x00000020U
|
||||
/* Waveform polarity */
|
||||
#define XTTCPS_CNT_CNTRL_POL_WAVE_MASK 0x00000040U
|
||||
/* Reset value */
|
||||
#define XTTCPS_CNT_CNTRL_RESET_VALUE 0x00000021U
|
||||
|
||||
/*
|
||||
* Interrupt Register Definitions
|
||||
*/
|
||||
|
||||
/* Interval Interrupt */
|
||||
#define XTTCPS_IXR_INTERVAL_MASK 0x00000001U
|
||||
/* Match 1 Interrupt */
|
||||
#define XTTCPS_IXR_MATCH_0_MASK 0x00000002U
|
||||
/* Match 2 Interrupt */
|
||||
#define XTTCPS_IXR_MATCH_1_MASK 0x00000004U
|
||||
/* Match 3 Interrupt */
|
||||
#define XTTCPS_IXR_MATCH_2_MASK 0x00000008U
|
||||
/* Counter Overflow */
|
||||
#define XTTCPS_IXR_CNT_OVR_MASK 0x00000010U
|
||||
/* All valid Interrupts */
|
||||
#define XTTCPS_IXR_ALL_MASK 0x0000001FU
|
||||
|
||||
/*
|
||||
* Constants
|
||||
*/
|
||||
|
||||
/* Maximum value of interval counter */
|
||||
#define XTTC_MAX_INTERVAL_COUNT 0xFFFFFFFFU
|
||||
|
||||
#endif /* ZEPHYR_DRIVERS_TIMER_XLNX_PSTTC_TIMER_PRIV_H_ */
|
||||
Loading…
Reference in a new issue