Add support for SMARTDMA to RT5xx SOCs. SMARTDMA ram banks will be
powered up, so code can be programmed into this region for the SMARTDMA
engine.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Adds CONFIG_STM32_ENABLE_DEBUG_SLEEP_STOP to allow debugger attaching in
sleep/stop mode of STM32 parts. Mainly useful for debugging. Move DBGMCU
from part-sepcific power.c to common soc_config.c. CONFIG_USE_SEGGER_RTT
depends on this as well.
Signed-off-by: Roland Lezuo <roland.lezuo@embedded-solutions.at>
Add node for VREF0 peripheral to LPC55S3X SOC DT
Clock VREF peripheral if status = okay in DT
Enable VREF on lpcxpresso55s36
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Enable clock control driver for NXP S32ZE SoCs and add clock sources
definitions for devicetree.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
PRE_KERNEL_1 is more suited for dealing with devices, so move out of
EARLY.
Verified on hardware and things seem to behave the same. Something was
changed since this was first introduced as this was not possible for
some reason.
Fixes#62627
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The ARM Cryptocell 310/312 IP is wrapped by Nordic specific registers.
It is organized as follows:
- Base address: Nordic wrapper
- Base address + 0x1000: ARM Cryptocell IP registers
Following more standard devicetree conventions, use a single node for
what is exposed as a single peripheral. The node contains 2 register
entries, one for the wrapper and a second one for the 3rd party IP.
Compatibles are used from more specific (nordic,cryptocell) to more
generic (arm,cryptocell-3xx).
Other minor fixes: peripheral is disabled by default (as it should be in
SoC dts files).
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Just like for the nrf52_bsim let's add helper kconfig symbols
which can be used to identify we are running in a target that
is compatible with the real HW but is not the real HW.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
This commit:
* adds the `CONFIG_SOC_GECKO_SERIES0` Kconfig option for Gecko Series 0
SoCs
* selects the proper `CONFIG_SOC_GECKO_SERIESx` option where it's currently
missing
Fixes#62806.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
Flash segments require VMA to proper work. Executing from LMA
is not possible. Current implementation did not take into account
runtime iterable rom sections that any application could implement.
In the above cenario and as reported in the issue below, ESP32 won't run
when those ROM sections are created in application level.
This change make sure all flash segments are properly mapped
accordingly.
Fixes#61834
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Selecting Low Power clock has the same result as selecting High
Performance clock (now IPLL). Therefore, the LP clock will be removed
from the list of available clocks on ACE family platforms.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Updating value of WOVRCO request bit in CLKCTL register according to the
documentation. Previus value was mask used for clock enabling.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
The iMX RT bootrom allows the user to load images into RAM regions from
flash by providing a correctly configured boot header. In particular, if
the boot header contains a load address within RAM, the bootroom will
automatically copy the image to the load address before executing it
Introduce CONFIG_NXP_IMX_RT_ROM_RAMLOADER to enable this feature. This
Kconfig will shift the LMA of a image built to run in a RAM region to
reside in the default FlexSPI boot region, which allows the image to be
loaded to the FlexSPI region using west. This is intended to simplify
development of applications executing from RAM on iMX RT based systems.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add check for device busy when CONFIG_PM_NEED_ALL_DEVICES_IDLE is
set to y because one or more devices may still in busy and causes
problem when system go into low power in Intel ISH platform.
Signed-off-by: Leifu Zhao <leifu.zhao@intel.com>
This is the final step in making the `zephyr,memory-attr` property
actually useful.
The problem with the current implementation is that `zephyr,memory-attr`
is an enum type, this is making very difficult to use that to actually
describe the memory capabilities. The solution proposed in this PR is to
use the `zephyr,memory-attr` property as an OR-ed bitmask of memory
attributes.
With the change proposed in this PR it is possible in the DeviceTree to
mark the memory regions with a bitmask of attributes by using the
`zephyr,memory-attr` property. This property and the related memory
region can then be retrieved at run-time by leveraging a provided helper
library or the usual DT helpers.
The set of general attributes that can be specified in the property are
defined and explained in
`include/zephyr/dt-bindings/memory-attr/memory-attr.h` (the list can be
extended when needed).
For example, to mark a memory region in the DeviceTree as volatile,
non-cacheable, out-of-order:
mem: memory@10000000 {
compatible = "mmio-sram";
reg = <0x10000000 0x1000>;
zephyr,memory-attr = <( DT_MEM_VOLATILE |
DT_MEM_NON_CACHEABLE |
DT_MEM_OOO )>;
};
The `zephyr,memory-attr` property can also be used to set
architecture-specific custom attributes that can be interpreted at run
time. This is leveraged, among other things, to create MPU regions out
of DeviceTree defined memory regions on ARM, for example:
mem: memory@10000000 {
compatible = "mmio-sram";
reg = <0x10000000 0x1000>;
zephyr,memory-region = "NOCACHE_REGION";
zephyr,memory-attr = <( DT_ARM_MPU(ATTR_MPU_RAM_NOCACHE) )>;
};
See `include/zephyr/dt-bindings/memory-attr/memory-attr-mpu.h` to see
how an architecture can define its own special memory attributes (in
this case ARM MPU).
The property can also be used to set custom software-specific
attributes. For example we can think of marking a memory region as
available to be used for memory allocation (not yet implemented):
mem: memory@10000000 {
compatible = "mmio-sram";
reg = <0x10000000 0x1000>;
zephyr,memory-attr = <( DT_MEM_NON_CACHEABLE |
DT_MEM_SW_ALLOCATABLE )>;
};
Or maybe we can leverage the property to specify some alignment
requirements for the region:
mem: memory@10000000 {
compatible = "mmio-sram";
reg = <0x10000000 0x1000>;
zephyr,memory-attr = <( DT_MEM_CACHEABLE |
DT_MEM_SW_ALIGN(32) )>;
};
The conventional and recommended way to deal and manage with memory
regions marked with attributes is by using the provided `mem-attr`
helper library by enabling `CONFIG_MEM_ATTR` (or by using the usual DT
helpers).
When this option is enabled the list of memory regions and their
attributes are compiled in a user-accessible array and a set of
functions is made available that can be used to query, probe and act on
regions and attributes, see `include/zephyr/mem_mgmt/mem_attr.h`
Note that the `zephyr,memory-attr` property is only a descriptive
property of the capabilities of the associated memory region, but it
does not result in any actual setting for the memory to be set. The
user, code or subsystem willing to use this information to do some work
(for example creating an MPU region out of the property) must use either
the provided `mem-attr` library or the usual DeviceTree helpers to
perform the required work / setting.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Xen-related Kconfig options were highly dependand on BOARD/SOC xenvm.
It is not correct because Xen support may be used on any board and SoC.
So, Kconfig structure was refactored, now CONFIG_XEN is located in
arch/ directory (same as in Linux kernel) and can be selected for
any Cortex-A arm64 setup (no other platforms are currently supported).
Also remove confusion in Domain 0 naming: Domain-0, initial domain,
Dom0, privileged domain etc. Now all options related to Xen Domain 0
will be controlled by CONFIG_XEN_DOM0.
Signed-off-by: Dmytro Firsov <dmytro_firsov@epam.com>
Move memory mapping of Xen node to Grant Table driver system init
function. After moving mapping we don't need anymore records of
xen-xen node into 'mmu_regions' array, so they were deleted from
all SoCs: Rcar Gen3/Gen4 and XenVM.
We need at least 16M of virtual address space to map memory of Xen
node, so the virtual memory sized has been increased to 32 MB, it
should be enough for basic use-cases and mapping of 16M mem region
of Xen node.
Unfortunately, after moving we also need to increase number of XLAT
tables. The previous code was more efficient if we talking about
usage of XLAT tables, because it mapped grant tables using a higher-
order table that allows mapping blocks of 2MB. And after the changes
is maps every 4KB page, so we need more XLAT tables.
Increase number of grant frames, it is needed to sync stage 1 and stage 2
memory mappings, previously we map only one page on stage 2 and further
usage of unmap regions can cause MMU translation errors.
Perform mapping stage 1 before mapping for stage 2 (add to physmap),
because right after stage 1 we can try to access memory and if it is
unmap in stage 2, error will be received during translation.
Note: Xen Grant Table driver doesn't use Zephyr Device Model.
Authored-by: Mykola Kvach <mykola_kvach@epam.com>
Co-authored-by: Oleksii Moisieiev <oleksii_moisieiev@epam.com>
Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
Configure SWO reference frequency to be the same as
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC. This should make all ST boards ready to
be used with SWO, without configuring any other devicetree property.
Tested with NUCLEO-L476RG and NUCLEO-H563ZI.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
This commit follows the parent commit work.
This commit introduces the following major changes.
1. Move all directories and files in 'include/zephyr/arch/arm/aarch32'
to the 'include/zephyr/arch/arm' directory.
2. Change the path string which is influenced by the changement 1.
Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
It doesn't make sense to keep the aarch32 directory in the
'arch/arm/core' directory as the aarch64 has been moved out.
This commit introduces the following major changes.
1. Move all directories and files in 'arch/arm/core/aarch32' to
'arch/arm/core' and remove the 'arch/arm/core/aarch32' directory.
2. Move all directories and files in 'arch/include/aarch32' to
'arch/include' and remove the 'arch/include/aarch32' directory.
3. Remove the nested including in the 'arch/include/kernel_arch_func.h'
and 'arch/include/offsets_short_arch.h' header files.
4. Change the path string which is influenced by the changement 1
and 2.
Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
This is a private kernel header with private kernel APIs, it should not
be exposed in the public zephyr include directory.
Once sample remains to be fixed (metairq_dispatch), which currently uses
private APIs from that header, it should not be the case.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Remove `threshold-reg-offset` DT property and implement them with static
inline functions in `reg_def.h`
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Add multi-device support in npcx adc driver since there is more than one
adc module in npcx4 series. And each adc's reference voltage might be
different, this CL introduces the `vref-mv` prop. to select its own
reference voltage.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Signed-off-by: Kate Yen <htyen@nuvoton.com>
The 'CCFG' (Customer Configuration) occupies 88 bytes in topmost flash
sector (8 KiB) and is by default always included in the final image.
This disables including CCFG part when building images for chain-loading
by the MCUboot bootloader.
Signed-off-by: Piotr Dymacz <pepe2k@gmail.com>
Introduce I2C target transfer using the PIO mode. Add an option
"target-pio-mode" in the yaml file, determined by the DTS, to dictate
whether I2C target transfer uses the PIO mode.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Disable the timeout setting when both the clock and data are
in a low state. This allows for I2C host clock stretching
without a timeout limit.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Added devicetree and Kconfig for EFR32MG12P433F1024GM68, needed for
the BRD4170A radio board by Silicon Labs.
Signed-off-by: Warren Buffer <warren.buffer78@gmail.com>
Created set of new functions for configure fir coefficients with support
for packed format. This allowed to make the dai_dmic_set_config_nhlt
function simpler.
Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
All fir filters have an identical set of registers so their definitions
were combined to simplify the code. From the dai_dmic_set_config_nhlt
function, a duplicate piece of code responsible for configuring fir was
separated into a new function.
Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
All PDM controllers have the same set of registers. Their definitions have
been merged to simplify the code.
Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
Add a new kconfig option to select which embedded
CPU we are targetting.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
The assert on L3_MEM_BASE_ADDR is incorrect, we need must convert
to uncached before use.
Fixes: ffd2121c65 ("soc: xtensa: intel_adsp: cavs: fix
power_down_cavs() signature")
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
To properly setup L1 exit timing this patch will use buffer interrupt
for HOST DMA and wait for Host HDA to actually start
First interrupt will clear all others.
Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
