Invoking `west sign` in `west build` accelerates twister because `west
build` is run in parallel, see rationale in superseded and very
different (CMake-based) PR #52942.
To maximize backwards compatibility:
- `west sign` is optional in `west build`
- `west flash` will sign (again) if any rimage --option is passed
Signed-off-by: Marc Herbert <marc.herbert@intel.com>
LNL uses MM_DRV_INTEL_ADSP_MTL_TLB to save / restore context.
This is exactly the same like on MTL. Enable PM for ACE 2.0 then.
Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
LNL platform is ACE 2.0 series with changes in shim registers and HW
features. Initial definition replicates MTL as much as possible, however
it will vary after enabling LNL platform.
Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Added a new watchdog driver which can handle a multiple wdt_dw instances
and can control the pause signal.
The mlt platform has three designware watchdogs, one for each core.
I decided to create a separate intel watchdog driver for the following
reasons:
1. All three devices share the same interrupt number. Each watchdog reports
an interrupt to the core to which it has been assigned. The same interrupt
number cannot be used by multiple devices in the device tree. So, it would
be assigned to only one device. The other dw watchdog devices would use
this assignment, even though it would not be described for them in the dt.
The interrupt handler function in dw watchdog checks the interrupt flag.
If the interrupt was connected to the first watchdog, and the second or
third watchdog signal an interrupt, the interrupt handler of the first
device would ignore it because it would not have set the interrupt flag.
The watchdog device don't knows anything about the existence of the others
devices.
2. The designware watchdog only supports a hardware pause signal. It cannot
be paused programmatically. On the mtl platform, there is a separate group
of control registers for all per-core watchdogs. There are GPIO-like
registers that allows control of a hardware pause signal for subordinate
watchdogs. This separate block is shared by all three watchdogs.
3. The base addresses of the subordinate watchdogs are read from the
aforementioned control registers. As a result, in the device tree we have
only one base address for the intel watchdog, which points to the pause
control registers and containing the base addresses of the subordinate
devices.
Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
It's best practice to run as little code as possible as root (especially
when listening to network ports). When not itself running as root
already, remote-fw-service.py has always tried to invoke cavstool.py
with "sudo". Unfortunately this looks like it never worked; at least not
on Ubuntu 22 where this commit was tested. Moreover it did not fail
immediately but mysteriously timed out without any useful error message.
- The first, most obvious bug was that "sudo" does not propagate
SIGKILL (and a few other signals), see "man sudo". Compare:
```
$ sudo sleep 30 &
$ kill $! # sudo propagates the TERM signal and sleep is terminated
$ sudo sleep 30 & sudoPID=$!
$ kill -KILL $sudoPID
$ ps xfao pid,ppid,pgid,sid,comm | grep -C 5 -e PID -e sleep -e sudo
```
Fix this by invoking proc.terminate() first before proc.kill().
proc.terminate() is more "polite" with cavstool even when not using
sudo.
- Second issue: when signals are sent to sudo, strace shows that its
signal handler invokes `getpgid()` and then ignores signals coming from
its own process group. `man sudo` states: "sudo will not relay signals
that were sent by the command it is running...", which seems related.
`start_new_session=True` option moves sudo to a different PGID which
stops sudo from ignoring signals from its remote-fw-service.py parent.
Signed-off-by: Marc Herbert <marc.herbert@intel.com>
Start using zephyr power management in cavs platform in a similar way
that is already done in ace. This commit only addresses the power off/on
sequence. Runtime power management is not implemented.
Signed-off-by: Jaska Uimonen <jaska.uimonen@linux.intel.com>
This reverts commit 7a85983ebc.
This commit was merged prematurely and is causing issues on multiple
platforms.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Now rimage can handle both cached and uncached addresses correctly,
ELF rewriting isn't needed any more.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Reusing existing code during CPU init at power gating exit.
Additional changes:
- replacing magic value for memctl and atomctl with more readable
definitions,
- using dedicated macros in place of asm inlines.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Now building twice back to back does not build anything the second time
when CONFIG_CLEANUP_INTERMEDIATE_FILES (which obviously breaks
incremental builds) is also turned off.
Fixes commit 2906d1aa51 ("soc/intel_adsp: Build bootloader with Zephyr")
Properly implementing custom commands requires BOTH
`add_custom_command()` and an `add_custom_target()` wrapper with some
careful DEPENDS wizardry between them.
https://cmake.org/cmake/help/latest/command/add_custom_target.html
> Use the add_custom_command() command to generate a file with
> dependencies.
The documentation of add_custom_command() also similarly refers to
add_custom_target()
When this is not done properly, the build is cursed in various, very
time-consuming ways which are not officially documented but here
instead:
https://samthursfield.wordpress.com/2015/11/21/cmake-dependencies-between-targets-and-files-and-custom-commands
Signed-off-by: Marc Herbert <marc.herbert@intel.com>
This is a bugfix. It uses the right storage label `slot0_partition` for
esp32s2. Note that this is already the case for esp32 and esp32s3.
This should address
https://github.com/zephyrproject-rtos/zephyr/issues/55286.
Signed-off-by: Ning Shang <syncom.dev@gmail.com>
Fixes the following warning:
cavstool.py:706: DeprecationWarning: There is no current event loop
asyncio.get_event_loop().run_until_complete(main())
Signed-off-by: Marc Herbert <marc.herbert@intel.com>
The watchdog is controlled by ll-scheduler and should not be resumed when
a core is bringing up. Watchdog pause control code was removed.
Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
Added intel_adsp_ipc_send_message_emergency function that allows to send an
ipc message notifying about emergency event, such as watchdog timeout.
Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
The non-maskable interrupt have no corresponding bit in INTERRUPT and
INTENABLE registers so its occurrence cannot be confirmed. Removed the code
that checked if the interrupt flag is set.
Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
rodata section for xtensa overrides the .ctors section
containing the constructor info and the _ZEPHYR_CTOR_LIST_.
Removes the ctor related linker script lines from the rodata
section of the ace linker script to ensure that the .ctors is
properly generated and placed when using the xcc-clang compiler.
Fixes#54730
Signed-off-by: Aastha Grover <aastha.grover@intel.com>
Temporary re-enabling interrupts before going to waiti. Right now
secondary cores don't have proper context restore flow and after leaving
D3 state core will return here and stuck. This is temporary workaround.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Adding additional core power-off before core is properly power-up after
power domains is wake up from power gaiting state.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This patch is moving common power configuration code outside of the
section only for the primary core. This should be enabled for all cores
and it was put there probably by mistake.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
When building with picolibc and gcc, the loops to do zeroing/copying
get replaced by gcc with calls to memset/memcpy. This fails this early in
the boot process and results in an illegal instruction exception.
Marking the variables being manipulated in the calls as volatile prevents
the compiler from optimizing the loops (replacing them with memset/memcpy).
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Disables allowing the python argparse library from automatically
shortening command line arguments, this prevents issues whereby
a new command is added and code that wrongly uses the shortened
command of an existing argument which is the same as the new
command being added will silently change script behaviour.
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
The parameter doc string for hda was incorrect as the parameters
had been updated to take the IP base address, block size, and stream id
instead. Updates all doc string comments to account for the change.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
The DMA API contract specifies that start/stop may be called multiple
times. Prior to adding power management this was perfectly fine as it was.
In adding power management, there are additional side effects that can
cause issues. Instead check the state of the channel prior to start/stop
and do nothing if already in the desired state.
Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
Intel DSP Communication Widget is a device for generic sideband
message transmit/receive between IPs in a SOC.
Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
This reverts commit 81908cd367.
This commit introduced a regression on SOF. Value of soc_cpus_active is
set by the core X it self in functions pm_state_set and
pm_state_exit_post_ops. soc_adsp_halt_cpu can by called only by the
primary core.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
The code used the name DFDSPBRCP referring to the DSP Boot / Recovery
Capability Pointer register from DSP Subsystem Capability / Status
Registers range. The address used, however, pointed to DSP Core Shim
(DSPCS) registers block. Changed define names to not be misleading.
Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
If defined(CONFIG_ASSERT) and !defined(CONFIG_ADSP_IMR_CONTEXT_SAVE),
build will fail as symbol "global_imr_ram_storage" is not defined.
Link: https://github.com/thesofproject/sof/issues/6896
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
ESP32 and ESP32-S2 HW clock are tied to DTS clock configuration.
This changes updates the default configuration to retrieve
this information from DTS.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Xtensa's ESP32 misses this base CCOUNT value, which causes wrong
arch_timing_freq_get() value reference.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Save FP user register and FP register file during context switch.
This change enables shared FP registers mode using CONFIG_FPU_SHARING.
Since there is no lazy stacking, the FPU registers will be saved regardless
of whether floating point calculations are performed in the threads when
CONFIG_FPU_SHARING is enabled. This require 72 additional bytes in the
stack memory.
Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
Add region calculations and implementation of
sys_mm_drv_query_memory_regions to pass calculated regions down
the line.
Signed-off-by: Jakub Dabek <jakub.dabek@intel.com>
Add virtual memory entry in dt to use as virtual space
regions for aplication.
Add virtual memory definition in adsp_memory.h
Signed-off-by: Jakub Dabek <jakub.dabek@intel.com>
This patch makes IMR context save an option that can be enabled. By
default FW, after D3 state transition, will be boot using normal flow.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
