This adds support for the async API for SAM0 SERCOM SPI using
DMA to drive the device. This implementation does the reload
for both transmit and receive in the receive DMA handler.
Doing this simplifies the implementation but means that the
transmit drains completely, resulting in the SPI clock pausing
between buffers while both are reloaded in the receive handler.
Tested with tests/drivers/spi/spi_loopback and several simple
programs monitored with a logic analyzer.
Signed-off-by: Derek Hageman <hageman@inthat.cloud>
Initial support for Microchip MEC1501 series is added to the tree.
Additional support for UART is also included. This SoC supports
two operational modes for interrupts (Direct and Aggregated). For
this commit, the direct capable interrupt are configured in direct
mode.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Add a Kconfig option to enable DMA for SPI with SOC_NRF52832 as long as
it being disabled due to Product Anomaly Notice (PAN) 58 is explicitly
overridden. This allows the SPIM driver to be enabled for the nRF52832
SoC for situations where PAN 58 is not a problem.
Signed-off-by: Andrew Fernandes <andrew@fernandes.org>
The init routines are the same for SAMD20, SAMD21 and SAMR21, so
move them into common/ to not have three copies of the same code.
Signed-off-by: Benjamin Valentin <benjamin.valentin@ml-pa.com>
The Atmel SAMD21 (and therefore also the SAMR21) comes with the same
RTC peripheral as the Atmel SAMD20.
Enable it in dts_fixup.h and enable it in the dts for samr21_xpro.
Signed-off-by: Benjamin Valentin <benpicco@googlemail.com>
Adds Atmel SAMR21 soc which is based on SAMD21, but with a AT86RF233
radio connected internally via SPI.
The AT86RF233 is not yet supprted by Zephyr at this point.
This code is very much copy & paste from atmel_sam0/samd21
Signed-off-by: Benjamin Valentin <benpicco@googlemail.com>
This commit renames the symbol CPU_HAS_SYSTICK to
CPU_CORTEX_M_HAS_SYSTICK, to look similar to all
other CPU_CORTEX_M_HAS_ options, and moves the
K-config symbol definition from arm/core/Kconfig to
arm/core/cortex_m/Kconfig.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
ARM SysTick timer is implemented by default in ARMv7-M
and Mainline ARMv8-M processors, so we include the
corresponding Kconfig symbol in arch/arm/core/cortex-M/Kconfig
and remove the selections from the Cortex-M SOCs.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
CPU_CORTEX_M does not need to be selected by Kconfig
symbols that already select a CORTEX_M variant.
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
The GPIO driver for the Intel Apollo Lake has so many pins it has to
export ten devices to shoehorn its one device into the GPIO API. The
current implementation uses the shared IRQ driver because these
pseudodevices all share one IRQ. However, since the GPIO driver is
aware of all the possible interrupt sources, it's smaller and faster
(and not even messy) to handle it internally, so this patch eliminates
the dependency on the shared IRQ driver.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
Add USART1 and LPUART1 nodes on stm32wb series.
Only these 2 ones are available for now on this series.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add GPIO support to stm32wb series.
Only ABCDE and H ports are available for now on this series.
Accordingly, update series dtsi file.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add support to stm32wb series in stm32 clock_control driver.
Ip is similar to stm32l4 one but AHB bus presacler is renamed
to "CPU1" and CPU2 and AHB4 prescalers should be defined.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add the initial SoC support for the STM32MP1 family. The code was
tested on STM32MP157c, but should work on any STM32MP1XX currently
available.
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@st.com>
Force soc.h to include the headers generated automatically
by DTS. In addition, force arm_mpu_regions.c to include
misc/slist.h for ARRAY_SIZE() macro. arm_mpu_regions.c
does not need to include soc.h (it is included indirectly
via arm_mpu.h)
Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
Add driver and device tree binding for the Low Power Inter-Integrated
Circuit (LPI2C) controllers found in the RV32M1 RI5CY SoC.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Same deal as in commit 4638652214 ("Kconfig: Use 'default' instead of
'def_bool' in Kconfig.defconfig files"), fixing new stuff that got
introduced since then.
Some symbols, like ALTERA_AVALON_PIO, are only defined in
Kconfig.defconfig files, and so need the def_bool.
Motivation (from the note at the end of
guides/kconfig/index.html#common-shorthands):
For a symbol defined in multiple locations (e.g., in a Kconfig.defconfig
file in Zephyr), it is best to only give the symbol type for the "base"
definition of the symbol, and to use 'default' (instead of 'def_<type>'
value) for the remaining definitions. That way, if the base definition
of the symbol is removed, the symbol ends up without a type, which
generates a warning that points to the other definitions. That makes the
extra definitions easier to discover and remove.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
This commit adds CAN support for nucleo F746zg.
Furtermore CAN was added in stm32f7.dtsi and pinmuc_stm32f7.h
CAN_RX: PD0, CAN_TX: PD1
Signed-off-by: Alexander Wachter <alexander.wachter@student.tugraz.at>
Missing quotes are accepted in some places for compatibility with the C
tools, e.g.
source no/quotes/Kconfig
menu Title
It looks broken though. Fix the two places in Zephyr that skip the
quotes. A style warning will be added.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
Allows to enable initial RTS/CTS hardware flow control
in the dts.
Co-authored-by: Benoit Leforestier <benoit.leforestier@gmail.com>
Signed-off-by: Georgij Cernysiov <g.cernysiov@elco-automation.de>
A parallel PCI implementation ("pcie") is added with features for PCIe.
In particular, message-signaled interrupts (MSI) are supported, which
are essential to the use of any non-trivial PCIe device.
The NS16550 UART driver is modified to use pcie.
pcie is a complete replacement for the old PCI support ("pci"). It is
smaller, by an order of magnitude, and cleaner. Both pci and pcie can
(and do) coexist in the same builds, but the intent is to rework any
existing drivers that depend on pci and ultimately remove pci entirely.
This patch is large, but things in mirror are smaller than they appear.
Most of the modified files are configuration-related, and are changed
only slightly to accommodate the modified UART driver.
Deficiencies:
64-bit support is minimal. The code works fine with 64-bit capable
devices, but will not cooperate with MMIO regions (or MSI targets) that
have high bits set. This is not needed on any current boards, and is
unlikely to be needed in the future. Only superficial changes would
be required if we change our minds.
The method specifying PCI endpoints in devicetree is somewhat kludgey.
The "right" way would be to hang PCI devices off a topological tree;
while this would be more aesthetically pleasing, I don't think it's
worth the effort, given our non-standard use of devicetree.
Signed-off-by: Charles E. Youse <charles.youse@intel.com>
The SYSCFG_CFGR1_PA11_PA12_RMP define is present even on packages where
the remap isn't strictly required. This commit makes the remap optional
based on a DT property.
Also fixes syntax error caused by a missing );.
Signed-off-by: Josef Gajdusek <atx@atx.name>
The i2s_cavs.c driver manipulates cache lines before commencing
any DMA transfers. With write-back cache, if the DMA receive
buffer is not aligned to the cache lines, the data around
the buffer will be invalidated and may never written to memory.
Since the driver takes an external memory slab as buffer and
there is no easy way to force cache line alignment on
the application side, set the cached region to write-through
to avoid potential issue.
Fixes#13223
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Update the files which contain no license information with the
'Apache-2.0' SPDX license identifier. Many source files in the tree are
missing licensing information, which makes it harder for compliance
tools to determine the correct license.
By default all files without license information are under the default
license of Zephyr, which is Apache version 2.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This macro is slated for complete removal, as it's not possible
on arches with an MPU stack guard to know the true buffer bounds
without also knowing the runtime state of its associated thread.
As removing this completely would be invasive to where we are
in the 1.14 release, demote to a private kernel Z_ API instead.
The current way that the macro is being used internally will
not cause any undue harm, we just don't want any external code
depending on it.
The final work to remove this (and overhaul stack specification in
general) will take place in 1.15 in the context of #14269Fixes: #14766
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
Rename reserved function names in arch/ subdirectory. The Python
script gen_priv_stacks.py was updated to follow the 'z_' prefix
naming.
Signed-off-by: Patrik Flykt <patrik.flykt@intel.com>
* the nsim host timer does not work as expected,
disable it, use cycle count to simulate timer tick
* optmize the freq definition of nsim_em
Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
