Use thread local storage to check whether or not a thread is running
in user mode. This allows to use threadptr to properly support tls.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Only clear the user stack to 0xAA if CONFIG_INIT_STACKS is
enabled. Otherwise, write 0x00 as if the stack is in BSS.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
During arch_kernel_init(), the interrupt stack is being
initialized. However, if the current in-use stack is
the interrupt stack, it would wipe all the data up to
that point in stack, and might result in crash. So skip
initializing the interrupt stack if the current stack
pointer is within the boundary of interrupt stack.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
We need to use the mmu spin lock when invalidating the cache during
tlb shootdown, otherwise it is possible that this happens when another
thread is updating the page tables.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
When the target has a cache way size (cache size / cache wasy) bigger
than the page size we have cache aliasing, since the number of bits
required by the cache index is bigger than the number of bits in the page
offset.
To avoid this problem we flush the whole cache on context switch or when
the current page table is changed.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
This enables tests/kernel/mem_protect/mem_protect to be tested
on Xtensa.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
This test requires architecture specific code to work.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Swap page tables at exit of exception handler if we are going to
be restored to another thread context. Or else we would be using
the outgoing thread's page tables which is not going to work
correctly due to mapping and permissions.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
When adding a thread to a memory domain, we need to also update
the mapped page table if it is the current running thread on
the same CPU. If it's not on the same CPU, we need to notify
the other CPUs in case the thread is running in one of them.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
After changing content of page table(s), it is needed to notify
the other CPUs that the page table(s) have been changed so they
can do the necessary steps to use the updated version. Note that
the actual way to send IPI is SoC specific as Xtensa does not
have a common way to do this at the moment.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
When kernel OOPS is raised, we need to actually go through
the process of terminating the offending thread, instead of
simply printing the stack and continue running. This change
employs similar mechanism to xtensa_arch_except() to use
illegal instruction to raise hardware exception, and going
through the fatal exception path.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Trigger exception on Xtensa requires kernel privileges. Add
a new syscall that is used when ARCH_EXCEPT is invoked from userspace.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
This extracts the printing of fatal exception information into
its own function to declutter xtensa_excint1_c().
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
There are known exceptions which are not fatal, and we need to
handle them properly by returning to the fixup addresses as
indicated. This adds the code necessary in the exception
handler for this situation.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
When MMU is enabled, we need some scratch registers to preload
page table entries. So update gen_zsr.py to that.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
This changes the TLB misses handling back to the assembly
in user exception, and any page faults during TLB misses to be
handled in double exception handler. This should speed up
simple TLB miss handling as we don't have to go all the way to
the C handler.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Add a header with architecture specific macros and
definitions that re used on userspace for stack
objects.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Userspace support for Xtensa architecture using Xtensa MMU.
Some considerations:
- Syscalls are not inline functions like in other architectures because
some compiler issues when using multiple registers to pass parameters
to the syscall. So here we have a function call so we can use
registers as we need.
- TLS is not supported by xcc in xtensa and reading PS register is
a privileged instruction. So, we have to use threadptr to know if a
thread is an user mode thread.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Simplify the logic around xtensa_mmu_init.
- Do not have a different path to init part of kernel
- Call xtensa_mmu_init from C
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Replace all autorefill helpers with only one that invalidates both,
DTLB and ITLB, since that is what is really needed.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
This is an older driver and didn't support the weak
arch_printk_char_out() hook, which is a link-time symbol that allows
logging to work from the first instruction. Some drivers can't do
that because they need an initialization step, but this one works
great.
Signed-off-by: Andy Ross <andyross@google.com>
This register alias was originally introduced to allow A0 to be used
as a scratch register when handling exceptions from MOVSP
instructions. (It replaced some upstream code from Cadence that
hard-coded EXCSAVE1). Now the MMU code is now using too, and for
exactly the same purpose.
Calling it "ALLOCA" is only confusing. Rename it to make it clear
what it's doing.
Signed-off-by: Andy Ross <andyross@google.com>
Rather than configuring in serial_wakeup sample, define LPUART1 wakeup
line in wl.dtsi file.
Additionally make few cosmetic changes to nucleo_wl55rj overlay in
serial wakeup sample.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
On STM32WB55 series, wakeup in stop mode is not supported.
Disable this state in order to support this sample.
Add comments to other sections of the configuration.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Serial wakeup feature was only working whe DBG in Stop mode setting
was enabled.
Add required changes to make it functional also when this configuration
isn't set.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
When playing with PM related applications, stm32cubeprogrammer is
useful to allow flashing even when SoC is in Stop mode.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
With the introduction of nrfx 3.0.0, values of `nrf_gpio_pin_drive_t`
constants may be defined differently, depending on the SoC family.
Since the nrf-pinctrl.h file is included also from dts files, it is
not possible to use there different definitions of `NRF_GPIO_PIN_*`
values based on Kconfig symbols that indicate given SoC family (as
Kconfig is processed after devicetree) so that those values could
still match `nrf_gpio_pin_drive_t` constants.
To solve this problem, the pinctrl_nrf driver now uses a lookup table
for mapping `NRF_GPIO_PIN_*` indexes to drive configuration values
required by the GPIO HAL.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
So far the driver first changed the configuration of the flash chip
and after that checked the signature of that chip. This could lead
to improper change of the chip configuration if the actually found
one was different than that specified in devicetree.
This commit reverses the order of these two initialization steps and
also restructures a bit the initialization code.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
After integration of nrfx 3.2.0, it is no longer needed to deinitialize
the nrfx_qspi driver to avoid increased power consumption when the QSPI
peripheral is idle. Now it is enough to call `nrfx_qspi_dectivate()`
when a given operation is done. The driver will automatically activate
the QSPI peripheral again when a next operation is requested.
This commit applies the following changes:
- `qspi_device_init` and `qspi_device_uninit` functions are replaced
by `qspi_acquire` and `qspi_release`, respectively; those handle
exclusive access to the QSPI peripheral and deactivation of it or
runtime device power management
- locking is removed from `qspi_send_cmd` as it is the resposibility
of the caller of that function
- `trans_lock` and `trans_unlock` functions are removed together with
the related semaphore as they are no longer needed
- checking of input parameters is moved from `qspi_erase` to its
caller, `qspi_nor_erase`
- `qspi_nor_pm_action` is refactored to properly handle locking of
the QSPI peripheral; checking of the `xip_enabled` flag is removed
from that function as now the call to `pm_device_is_busy()` covers
that (when XIP is enabled, the device is kept indicated as busy)
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Consistently use `res` for results of calls to nrfx functions
and `rc` for Zephyr return codes, to avoid mixing up those two
and for example calling `qspi_get_zephyr_ret_code()` for a value
that is already a Zephyr return code. Correct also such call in
`qspi_nor_write()`.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This is a follow-up to commit 7a83724e0f.
There is no reason to mark that many GPIO lines as reserved on this
board. And doing so causes several existing tests to fail as they
are configured to use some of those now unavailable GPIO lines.
Limit reservation to the lines that actually cannot be used as
GPIOs without changes in the default configuration of the board
or its physical modification (via solder bridges), i.e.:
- XL1 and XL2 (connections for the 32.768 kHz crystal)
- NFC1 and NFC2 (NFC antenna connections)
- RESET
- TXD and RXD (lines used by the console UART)
- QSPI lines: CS, CLK, and DIO0-3
Provide names for all the GPIO lines that are described on the board.
Even for the reserved ones, so that it is clear why they are reserved.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
After entering the Deep Power-down mode, some flash chips ignore all
commands except from the one that releases the chip from the DP mode
and it is not possible to successfully read their Status Register then.
Since the QSPI peripheral tries to read this register when it is being
activated, it consequently fails to send the actual command that would
release the flash chip from the DP mode if that is to be done right
after QSPI initialization.
Prevent this problem by performing the QSPI activation with all pins
disconnected. This causes that the Status Register value is read as
all zeros and allows the activation to always finish successfully,
and the RDPD command to be properly sent.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
`CONFIG_BT_CTLR_ADV_DATA_CHAIN` is a Zephyr Controller exclusive.
Use the max length instead to decide if we should add more data.
The motivation for the change is that tests/bsim/bluetooth/host/adv/chain
does not pass with Nordic's Softdevice Controller because of this.
Signed-off-by: Jonathan Rico <jonathan.rico@nordicsemi.no>
Some shell modules were disabled in one of previous commits.
Tests in this folder requires mcuboot shell command.
Enable it with CONFIG_MCUBOOT_SHELL.
Signed-off-by: Grzegorz Chwierut <grzegorz.chwierut@nordicsemi.no>
TF-M only suports floating point in IPC model, not the SFN model.
Since floating point is a basic feature of the architecture and TF-M
has the limitation it makes more sense for the dependency to exist in
TF-M and and limit the TF-M model choice instead of limiting the
option to enable floating point.
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
Add support for the WeAct Studio STM32G431 Core board. Note that this
board does not support USB-C PD in its default configuration. See the
board documentation for the necessary hardware reconfiguration.
Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
Add support for the WeAct Studio STM32G431 Core Board.
Tested with:
- `samples/basic/blinky`
- `samples/basic/button`
Flashed samples using dfu-util.
Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
Those configuration settings should never be part of driver Kconfig file.
Drop them, since they can easily result in Kconfig symbol circular
dependency error.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
