There are duplicated names specified in per-board YAML files.
This change will allow distinguishing boards in software that
presents the pretty names and not the raw names of boards.
Signed-off-by: Wojciech Sipak <wsipak@antmicro.com>
Enable ticket spinlock on nsim SMP board as they are
naturally vulnerable to spinlock unfairness due to
SMP nSIM way of work.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
Fix typo in nsim_hs6x_smp_12cores platform name (as previously
we had nsim_hs5x_smp_12cores platform mentioned two times)
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
This is coming from devicetree and corrosponds to what we have in the
dts/bindings/vendor-prefixes.txt file.
This will allow for static filtering, especially with twister, i.e. no
need to build anything to know the vendor of a board
All of the vendor data was extracted automatically from the devicetree,
so some platforms might not have the right vendor or no vendor at all
right now, we need to fix some of the DTS information or do this
manually to get this 100% correct. But we are close.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
- Updated basic samples READMEs to use the new zephyr:code-sample::
directive. Dropped "-sample" suffix that's not required anymore now
that samples have their own namespace.
- Updated all references to the samples to use the :zephyr:code-sample:
role. Checked and updated the wording of said references to account
for the fact that samples should not have "... sample" in their name
anymore.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Make make UART IRQ line number configurable in nSIM
nsim-uart-ns16550.dtsi DTS helper.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
Actual DCCM size is 100000 in nsim_hs_mpuv6, nsim_hs
and nsim_hs3x_hostlink, but their nsim property is
40000. Now fixed the difference to avoid data access
to unpopulated region during picolibc malloc heap init.
In minimal libc, it is set not using malloc as default.
Signed-off-by: Siyuan Cheng <siyuanc@synopsys.com>
The init infrastructure, found in `init.h`, is currently used by:
- `SYS_INIT`: to call functions before `main`
- `DEVICE_*`: to initialize devices
They are all sorted according to an initialization level + a priority.
`SYS_INIT` calls are really orthogonal to devices, however, the required
function signature requires a `const struct device *dev` as a first
argument. The only reason for that is because the same init machinery is
used by devices, so we have something like:
```c
struct init_entry {
int (*init)(const struct device *dev);
/* only set by DEVICE_*, otherwise NULL */
const struct device *dev;
}
```
As a result, we end up with such weird/ugly pattern:
```c
static int my_init(const struct device *dev)
{
/* always NULL! add ARG_UNUSED to avoid compiler warning */
ARG_UNUSED(dev);
...
}
```
This is really a result of poor internals isolation. This patch proposes
a to make init entries more flexible so that they can accept sytem
initialization calls like this:
```c
static int my_init(void)
{
...
}
```
This is achieved using a union:
```c
union init_function {
/* for SYS_INIT, used when init_entry.dev == NULL */
int (*sys)(void);
/* for DEVICE*, used when init_entry.dev != NULL */
int (*dev)(const struct device *dev);
};
struct init_entry {
/* stores init function (either for SYS_INIT or DEVICE*)
union init_function init_fn;
/* stores device pointer for DEVICE*, NULL for SYS_INIT. Allows
* to know which union entry to call.
*/
const struct device *dev;
}
```
This solution **does not increase ROM usage**, and allows to offer clean
public APIs for both SYS_INIT and DEVICE*. Note that however, init
machinery keeps a coupling with devices.
**NOTE**: This is a breaking change! All `SYS_INIT` functions will need
to be converted to the new signature. See the script offered in the
following commit.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
init: convert SYS_INIT functions to the new signature
Conversion scripted using scripts/utils/migrate_sys_init.py.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
manifest: update projects for SYS_INIT changes
Update modules with updated SYS_INIT calls:
- hal_ti
- lvgl
- sof
- TraceRecorderSource
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
tests: devicetree: devices: adjust test
Adjust test according to the recently introduced SYS_INIT
infrastructure.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
tests: kernel: threads: adjust SYS_INIT call
Adjust to the new signature: int (*init_fn)(void);
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Yaml description for simulators should contain simulation_exec
telling which tool to use. nsim_em11d was missing this entry
causing twister to only build but not execute tests on this
platform. Value from other nsims was used.
Signed-off-by: Maciej Perkowski <Maciej.Perkowski@nordicsemi.no>
Enable FPU for nsim_sem_mpu_stack_guard to fix zdsp.basicmath.fpu
failure due to lack of FPU option. Add FPU feature to its related
mdb.args, also for nsim_sem and nsim_em7d_v22 boards.
Signed-off-by: Siyuan Cheng <siyuanc@synopsys.com>
To run zdsp tests on nsim_sem and nsim_em7d_v22, FPU feature
is needed to be added in their nsim.props file.
Signed-off-by: Siyuan Cheng <siyuanc@synopsys.com>
Allow cross-compile toolchain for all ARC target which support zephyr
toolchain.
This aligns the behavior between ARC targets - as some of them
were supporting zephyr toolchain but weren't supporting cross-compile
toolchain (which wasn't actually true).
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
The XY Memory is a feature commonly found in DSP processors to increase
the DSP performance. The XY component allows a ARC processor to
implicitly load source operands and store results into a closely coupled
memory using a single instruction.
Add XY memory for ARC EM9D/EM11D processors including em_starterkit,
em_starterkit_em11d. emsdp_em9d, nsim_em, iotdk.
Signed-off-by: Siyuan Cheng <siyuanc@synopsys.com>
We mark MPU existing for nSIM HS SoC, but doesn't enable
it for nsim_hs board. Fix that.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
Provide the information as part of the board yaml file, this way we will
know what binary to check for.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Add XIP support with MWDT toolchain. To have it proper tested
add separate nsim platforms for XIP (flash + sram) and
non-XIP (sram) memory organization in addition to existing
nsim_hs platfor with CCMs (ICCM + DCCM) memory organization.
This PR also enables MPU for all nsim hs3x based platforms
(like we previously enabled it for qemu_arc_hs) to have proper
memory regions permissions.
Signed-off-by: Nikolay Agishev <agishev@synopsys.com>
Update cmake related files that are used by simulators to use
CONFIG_MP_MAX_NUM_CPUS instead of CONFIG_MP_NUM_CPUS as we work to
phase out CONFIG_MP_NUM_CPUS.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
Needed for proper filtering based on type in twister.
Sometimes we do not want to run a test in a simulator.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
As we've finally switched to 0.15.0 Zephyr SDK in upstream
verification we can enable zephyr toolchain for all ARC HS5x
targets.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
Update nsim / mdb options of nsim_hs6x and nsim_hs6x_smp
to be closer to default hs68 templates.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
Header was not used, so remove it. Add other necessary includes as part
of the removal.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
ICI (Inter-Core Interrupt Unit) interrupts and priorities were hardcoded
in C files. This patch moves this information to Devicetree and updates
code to make use of it.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Use Devicetree to describe secure timer0 instead of hardcoding values in
<soc.h>.
DT files have been structured to match the following requirements: In
case of sectimer0 - it's should be only enabled for:
- emsdp_em7d_esp.dts
- em_starterkit_em7d.dts
- nsim_sem_mpu_stack_guard.dts
- nsim_sem.dts
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Now that serial drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.
Typically the Kconfig.defconfig* will blindly enable a
sensor and not respect the devicetree state of the serial.
Additionally we can get problems with prj.conf/defconfig
getting incorrectly overridden.
Signed-off-by: Kumar Gala <galak@kernel.org>
Do not check for exact SoC to pass '--cores=${CONFIG_MP_NUM_CPUS}'
options to runners an pass it unconditionally instead.
That preventis from issues when adding new SoC/board.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
The ns16550 flags reg-shift property as optional. In case it is not
supplied, the ns16550 driver relies on a value defined in <soc.h>, or,
by default it takes 4 (shift by 2).
This patch adds the property to all ns16550 nodes, with the following
values:
- 2 if SoC did not have any custom value defined by
UART_REG_ADDR_INTERVAL (corresponds to 1 << 2 = 4)
- If SoC defined DEFAULT_REG_INTERVAL (snps_arc_iot/it8xxx2), use such
value (4=2, 2=1, 1=0).
These changes will allow simplifying the ns16550 driver.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
nSIM SMP simulation is s bit slower than single-core one, so
let's increase timeouts for nsim_hs5x_smp platforms as we have for
nsim_hs_smp and nsim_hs6x_smp
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
Setup peripheral and NOC apertures to make hs5x and hs6x configurations
runnable on real HW (HAPS).
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Use correct gfrc version in nsim args for mdb_hs6x_smp board.
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Add nSIM-based (simulator) boards with
* nsim_hs5x - single core ARCv3 HS5x 32 bit CPU
* nsim_hs5x_smp - SMP, two core ARCv3 HS5x 32 bit CPU
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
In order to bring consistency in-tree, migrate all boards code to the
new prefix <zephyr/...>. Note that the conversion has been scripted,
refer to zephyrproject-rtos#45388 for more details.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Currently we use incorrect memory layout for SMP boards as
we put data (which need do be accessible from all cores) to
DCCM which is private for each CPU core.
This works for nSIM which doesn't simulate CCMs (as we don't pass
corresponding nSIM options for SMP configurations) however
it won't work if we run that code on real HW (we want to achieve
that nSIM configurations are also runnable on HAPS - FPGA platform).
Let's fix that issue by using DDR instead of CCMs for SMP
configurations (nsim_hs_smp and nsim_hs6x_smp).
While I'm at it - switch UP HS6x configuration (nsim_hs6x)
for DDR usage instead of CCMs - to make that configuration closer
to the HAPS config we have.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
nSIM SMP simulation is s bit slower than single-core one, so
let's increase timeouts for nSIM SMP platforms.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
