Add binding for sitronix ST7796s, a MIPI DBI display controller
supporting up to 320x480 displays at 18 BPP
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
For now DSI settings are hard-coded for the specific
LCD module used on the STM32H747I Discovery board
Signed-off-by: Erik Andersson <erian747@gmail.com>
Exhibit Renesas LCD controller's driver implementation. The driver
is intended to employ the controller in the continuous mode so
it can drive display panels in the parallel RGB mode.
Signed-off-by: Ioannis Karachalios <ioannis.karachalios.px@renesas.com>
Display is not working on STM32F429i-DISC1 board because
display_blanking_off() needs to be sent to ILI9341 device, but it's sent
to LTDC instead which does not implement it.
This patch adds a LTDC DT property that provides the pHandle of the
display's own controller so that display_blanking_off/on are forwarded to
it when they are called by an application.
Signed-off-by: Abderrahmane Jarmouni <abderrahmane.jarmouni-ext@st.com>
Convert ili9xxx display drivers to use MIPI DBI API. Due to the fact
this change requires a new devicetree structure for the display driver
to build, required devicetree changes are also included in this commit
for all boards and shields defining an instance of an ili9xxx display.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Utilize a code spell-checking tool to scan for and correct spelling errors
in all files within the dts/bindings/bluetooth, can, dac and display.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
Adding driver for GC9A01A 240x240 based LCD displays.
Should be working with GC9C01 as well (untested).
Signed-off-by: Martin Kiepfer <mrmarteng@teleschirm.org>
Add support for uc8175 display driver. uc8175 has a slightly
different command/data length requirements for certain registers,
namely TRES and PTL, compared to uc8176/uc8179
This commit refactors the driver code and such that setting TRES and PTL
registers are now done by function pointers provided by config->quirks,
by the same token as how it is done for setting CDI register
Signed-off-by: Xiao Qin <xiaoq@google.com>
Determine sh1106 from the `compatibility` value instead of
the SSD1306_CONTROLLER_TYPE setting.
Change the settings in `boards/shields/ssd1306/sh1106_128x64.overlay`
to follow this change.
Remove the SSD1306_CONTROLLER_TYPE from its Kconfig.defconfig,
and set the `compatibility` to `sinowealth,sh1106`.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
When multiple devices are connected, the SSD1306_REVERSE_MODE setting
cannot switch for each device.
Add an equivalent setting to the devicetree properties to replace it.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Seems like the SSD1306 controller needs a bit of time after power up
before it can take i2c commands. This causes problems with
microcontrollers that have no other delays in the startup sequence, like
rpi_pico.
There's currently no good way of modeling this in Zephyr right now, and
there's also no clear indication of how much time the device needs in
the datasheet that I could find, but it seems like 10ms is enough for
that to start reliably so add a delay in the ssd1306 init function to
ensure that at least that time has passed from system power up.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Add driver for HX8394 TFT LCD controller. This controller is driven via
MIPI DSI, and is configured for a 720x1280 display
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The NXP Pixel pipeline engine (PXP) is a 2D DMA engine capable of
accelerating display rotation, color space conversion, and limited
2D blending operations. This DMA driver only supports rotation of a
framebuffer, via a set of custom dma_slot values. Only DMA channel 0
is supported or utilized.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add support for RM67162 MIPI display controller. This controller
is configured to run in MIPI command/DBI mode, driving a 400x392 OLED
display.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The display controller supports software reset and the driver already
implements it. Therefore it's not necessary to require a reset gpio in
device tree.
Signed-off-by: Caspar Friedrich <c.s.w.friedrich@gmail.com>
This driver implement basic functions of ili9342c controller
which comes mostly with IPS displays.
Signed-off-by: Mohamed ElShahawi <ExtremeGTX@hotmail.com>
Add support for partial refresh profiles. This makes it possible to
use partial refresh on generation 2 devices which are able to store
partial refresh LUTs in OTP.
Partial refresh is only enabled if a partial profile has been
provided. The display will use the full refresh profile if in this
case.
Devices that need custom LUTs and voltages can specify them separately
for the full and partial profiles. The controller will be reset when
changing profiles which means that profiles always override the
default reset values. This means that it is, for example, possible to
use default values and LUTs from OTP for a full refresh and a custom
profile for partial refreshes.
For example, to use a GoodDisplay GDEY027T91 with partial refresh
simply use the following device tree fragment:
display: ssd1680@0 {
compatible = "solomon,ssd1680";
spi-max-frequency = <4000000>;
duplex = <SPI_HALF_DUPLEX>;
reg = <0>;
dc-gpios = <&arduino_header 15 GPIO_ACTIVE_LOW>;
reset-gpios = <&arduino_header 14 GPIO_ACTIVE_LOW>;
busy-gpios = <&arduino_header 13 GPIO_ACTIVE_HIGH>;
/* Enable the built-in temperature sensor */
tssv = <0x80>;
width = <264>;
height = <176>;
/* Enable partial refresh using built-in LUT */
partial {
};
};
Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
Update the device tree bindings for the SSD16xx driver to make it
possible to specify multiple refresh profiles.
The only profile currently supported is the 'full' profile.
Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
The SSD16xx driver currently provides basic support for most chips in
the Solomon Systech SSD16xx range of e-paper drivers. We currently use
the SSD1608, SSD1673, SSD1675A, and SSD1681 in various boards
supported by Zephyr.
The main user-facing difference between the various SSD16xx chips is
the resolution they support (sources & gates), but there are other
differences as well. For example:
* 8 or 16 bits used to represent x coordinates
* 8 or 16 bits used to represent y coordinates
* Differences in refresh configuration (SSD16XX_CMD_UPDATE_CTRL2)
* Differences in LUT sizes
The driver currently assumes that the user specifies the number of
bits used to describe coordinates. However, as we add support for more
chips, more of the differences will become apparent and need
workaround.
Comparing data sheets from different chips in the SSD16xx range
suggests that there are (at least) two different generations
present. These differ in the size of the LUTs they expect and the way
they handle partial refresh. This impacts register layout where
SSD16XX_CMD_UPDATE_CTRL2 uses bit 3 selects "mode 2" whereas older
devices uses this for a mode referred to as "initial".
In order to add support for partial refresh in newer devices, we need
to be able to distinguish between the different generations of the
chip. It might be possible to add a DT property to indicate the
revision, but that seems like a bit of an anti-pattern and it would be
hard for users to specify the correct chip generation.
This change introduces chip-specific compatible strings instead of the
generic SSD16xx. There is unfortunately clear pattern that can be used
to distinguish different generations, so the full chip name must be
specified. A benefit of this is that we don't need to specify the
width of the fields describing coordinates in device trees.
Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
Update LTDC driver to use LCDIF bindings, to simplify bindings
between LCD interface controller IP blocks.
Boards supporting the LTDC are also updated to use the properties as
declared by the new lcd controller binding
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Update MCUX ELCDIF driver to use new LCDIF bindings. This
update also adds support for configuring the root clock of
the ELCDIF module based on the pixel-clock property to the
RT11xx SOC clock init, as this SOC series has this IP block
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Update DCNANO LCDIF IP to use shared lcd interface binding. This
requires changes to the RT5xx SOC and RT595 EVK, as this SOC
uses the LCDIF IP, and configures the clock for it based off
the new pixel-clock property.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add common LCD interface binding. This binding captures the
following properties, which are shared between multiple LCD interface
IP blocks:
- VSYNC/HSYNC pulse width
- Vertical/Horizontal front and back porch
- HSYNC,VSYNC,data enable, and pixel clock polarity flags
- pixel clock frequency
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Use the LTDC in combination with the DSI HOST makes the pinctrl obsolete.
DSI HOST has dedicated pins.
Signed-off-by: Rico Ganahl <rico.ganahl@bytesatwork.ch>
Introduce driver for NXP DCNANO LCDIF (lcd interface) peripheral,
present on iMX.RT500. Currently this driver only supports updating
the primary framebuffer, and does not implement support for the cursor
buffer present on this IP.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Fix all line-length errors detected by yamllint:
yamllint -f parsable -c .yamllint $( find -regex '.*\.y[a]*ml' ) | \
grep '(line-length)'
Using a limit is set to 100 columns, not touching the commandlines in
GitHub workflows (at least for now).
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Fix all brackets errors detected by yamllint:
yamllint -f parsable -c .yamllint $( find -regex '.*\.y[a]*ml' ) | \
grep '(brackets)'
Default config is to have no spaces inside brackets, changed few
documentation strings as well that refered to lists even though the
linter does not care about those.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Add rgb-is-inverted option to indicate module's pixel-format is
inverting from MADCTL settings of ST7735R controller.
This option intends to implement a workaround for LCD modules
that is the actual screen color was different (inverted)
from the RGB setting in MADCTL property.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
DTS property attributes are (by default) not required.
Explicitly specifying `required: false` is redundant.
Perhaps a warning to that effect would be useful.
Signed-off-by: Chris Friedt <cfriedt@meta.com>
Convert the device to be Devicetree based. Adjusted tests and other
areas that were using old Kconfig properties.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Some custom refresh profiles need to set the PLL and VDCS
registers. Add them as optional DT properties.
Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
Add support for overriding display LUTs in the UC81xx driver. This
makes it possible to use different LUTs for the full and partial
refresh profiles.
Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
Add a separate profile for partial refreshes. This makes it possible
to specify a separate refresh configuration for partial and full
refreshes.
The driver now transitions to full refresh mode when blanking is
turned on. It transitions back to partial refresh mode when there is a
write while blanking is off.
Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
Introduce the concept of refresh profiles which are specified as a
child node in the device tree. This makes it possible to use different
overrides for different types of refreshes (full/partial).
The only profile that is currently supported is the "full" profile.
Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
The SSD16xx driver currently hard-codes a couple of register overrides
that aren't relevant or even correct for many devices. Make them
optional device tree properties instead.
Note that this changes the behavior for panels that expect
SSD16XX_CMD_DUMMY_LINE and SSD16XX_CMD_GATE_LINE_WIDTH to be set by
the driver. This fixes a bug where the incorrect value
was written to all SSD16xx panels except for GDEH0213B1 and GDEH029A1.
The overlay files for devices that need dummy line and gate line width
to be specified have been updated as a part of this commit.
Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
The OTP in most SSD16xx-based displays normally contain default
VCOM/GDV/SDV values. Make all of these optional in the device tree.
Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
The UC8176 and UC8179 chips that exist in tree have subtly different
register layouts. Use separate compatible strings for these chips and
a quirks structure that describe device-specific behavior.
Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
The GD7965 driver is really just a vendor name for the UltraChip
UC8179. Rename the driver to UC81xx since there are other chips in the
family (e.g., the UC8176) with an almost identical register interface.
Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
Some panels using this driver don't provide tcon/cdi/pwr/softstart
values in their reference code. It is normally expected that the right
values will be loaded from OTP in such cases. Make these values
optional to support such panels.
Signed-off-by: Andreas Sandberg <andreas@sandberg.uk>
All in tree device drivers use some form of DEVICE_DT_GET
so we no longer need to require label properties.
Signed-off-by: Kumar Gala <galak@kernel.org>
All in tree device drivers use some form of DEVICE_DT_GET
so we no longer need to require label properties.
Signed-off-by: Kumar Gala <galak@kernel.org>
