Some configurations have the system timer driver hardwired in.
Let's make them compatible with CONFIG_SYS_CLOCK_EXISTS=n.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
This board has a single instance of EMAC connected to a NXP TJA1103
Ethernet PHY. Currently, there is no driver for this PHY and its
pin strapping configuration allows to use it without software
configuration, so EMAC is configured as fixed link.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Change the eth-phy definition so that the phy is pointed by a phandle
rather than a child node, make the phy device a child of mdio. This
makes more sense from a devicetree hirearchy where the phandles have to
be initialized before the device itself, allows keeping the priorities
in check with CHECK_INIT_PRIORITIES.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Make ethernet phys childs of the mdio device and move the mdio device up
a level on the tree. That makes the device hierarchy coherent with the
required initialization priority and allows keeping the sequence in
check with CHECK_INIT_PRIORITIES.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
This updates Silicon Labs EFR32BG BRD4184 (Thunderboard BG22) board
documentation, adding information about the 'B' revision.
Signed-off-by: Piotr Dymacz <pepe2k@gmail.com>
This adds basic support for 'B' revision of the Silicon Labs EFR32BG
BRD4184 (Thunderboard BG22) board. Due to missing drivers, some of the
on-board peripherals are currently unsupported:
- Silicon Labs Si7021 relative humidity and temperature sensor
- Vishay VEML6035 ambient light sensor
- Knowles SPK0641HT4H-1 MEMS microphones
- TDK InvenSense ICM-20648 6-axis inertial sensor
Signed-off-by: Piotr Dymacz <pepe2k@gmail.com>
Configure the NXP FS26 SBC on the LPSPI3 bus and enable it by default on
this board configuration so that there is no need to start the FS26 in
debug mode.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Configure LPSPI instances on this board. All of them are routed with SDI
and SDO data pins inverted.
Enable SPI tests without DMA support for the moment.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
This commit fixes the definition of the green led pin
on the nucleo-L552ZE-Q board
The new port/pin for this led (LED1) can be confirmed
using docs from os.mbed.com for this board.
Additionally I tested it on my own hardware.
Also updated the LD2 entry in the docs which was incorrect.
Signed-off-by: Łukasz Hejnak (LeHack) <lehack-ghub@lehack.pl>
Currently on zephyr, RAIL is used only for bluetooth. RAIL library is
needed to use efr32 radio regardless of the protocol used. We add
SOC_GECKO_USE_RAIL kconfig option to indicate if we use radio.
FPU is needed when using RAIL, we configure it if SOC_GECKO_USE_RAIL
is set.
Signed-off-by: Antoine Bout <antoine.bout@silabs.com>
Rename the phy-dev property with phy-handle to match the Linux
ethernet-controller binding and move it up to ethernet.yaml so that it
can be used by other drivers.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Now that vendor name in board compatible is meant to be actually used,
it should be properly filled.
Update when not correct and don't put any name when vendor is not known
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Add zephyr_udc0 nodelabel to allow building all USB device samples
for adafruit_feather_m0_basic_proto board out of the box.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
The device tree file for up_squared includes the base dts file
for Apollo Lake which only defines 1 CPU. UP Squared have
different SKUs with different CPUs, and overall has a minimal
of 2 CPUs. So amend the up_squared device tree overlay to have
2 CPU nodes.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Currently, mr_canhubk3 is enabling GPIO by default.
GPIO will be built even if it is not necessary.
Update to enable it for supporting CAN transceiver
when CAN is enabled.
Signed-off-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
Add rk055hdmipi4ma0 shield, which uses an HX8394 TFT LCD controller and
GT911 touch IC. This shield is enabled on the RT595 and RT1170 EVK,
which have 40 pin FFC interfaces capable of connecting to the display.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
So far pin identifiers were named after CN7 and CN10 connector names on
Nucleo-64 boards. In case of Nucleo-144 there are ST Morpho connectors on
both sides, but bigger (up to 72 instead of 38 pins on each side). First 38
pins out of 72 on each side usually map to the same pins (e.g. PA5 being
13th pin on right ST Morpho connector). This means that single ST Morpho
connector definition will suffice.
Leaving CN7 and CN10 (name of pin headers on Nucleo-64 boards) is confusing
in context of Nucleo-144 boards, since corresponding pin headers are named
CN11 and CN12.
Rename:
* s/ST_MORPHO_CN7_/ST_MORPHO_L_/
* s/ST_MORPHO_CN10_/ST_MORPHO_R_/
so that pin identifiers make more sense in context of Nucleo-144 boards.
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
The 'west flash' command allows specifying the port where the target is
attached via the '--serial' option, allowing users to set the USB serial
port for flashing. However, the 'stm32f746g_disco' script file currently
ignores the _ZEPHYR_BOARD_SERIAL variable set by this option, preventing
effective port specification.
This commit fixes it by correctly setting the openocd adapter serial
when _ZEPHYR_BOARD_SERIAL variable is set, enabling proper USB serial
port specification during flashing.
Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org>
Update to shim driver compatible with the hardware block
in S32K344. Configure the pins before initializing I2C
to avoid happening bus busy.
Signed-off-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
Reuse existing MCUX-based shim driver for FlexCAN.
Enable flexcan0 for Zephyr canbus to run tests.
Signed-off-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
The `cpu-power-states` property needs to be defined at SoC dts files,
since it's a property of the SoC, not board.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Adds driver for pwm on xmc4xxx using Capture Compare Unit 8 (CCU8)
module. There are two CCU8 nodes with each one having four slices.
Each slice has two output channels.
Unlike CCU4, this module can generate complementary high-side/low-side
signals for each output channel. A variable dead time can be added
during the off to on transitions to make sure that the
high-side/low-side signals are not on at the same time.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
Adds driver for pwm on xmc4xxx using Capture Compare Unit 4 (CCU4)
module. There are four CCU4 with each one having four channels
Thus it's possible to have up to 16 pwm output signals. The output of
each channel can only be connected to a specific port/pin. The possible
connection and gpio configurations are defined using pinctrl.
The CCU4 module also has a capture mode. Capture support will be added
in the future.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
Add initial version of Infineon CAT1 counter driver
Add initial version of binding file for Infineon
Add counters to psco6 dtsi
Add external trigger pin that runs counter
Signed-off-by: Pavlo Havrylyuk <pavlo.havrylyuk@infineon.com>
This is the initial Zephyr support for Intel SoC FPGA Agilex5 support.
Agilex5 has dual-core 64-bit ARM Cortex*-A55 and dual-core 64bit
ARM Cortex*-A76.
The Zephyr will need to be loaded by Intel Arm Trusted Firmware (ATF).
Agilex5 Zephyr boot flow:
FSBL:ATF BL2(EL3) -> ATF BL31(EL3) -> OS:Zephyr(EL1)
Intel ATF can be loaded from:
https://github.com/altera-opensource/arm-trusted-firmware.git
Signed-off-by: Teik Heng Chong <teik.heng.chong@intel.com>
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Refactor the ESP32 target SOCs together with
all related boards. Most braking changes includes:
- changing the CONFIG_SOC_ESP32* to refer to
the actual soc line (esp32,esp32s2,esp32s3,esp32c3)
- replacing CONFIG_SOC with the CONFIG_SOC_SERIES
- creating CONFIG_SOC_FAMILY_ESP32 to embrace all
the ESP32 across all used architectures
- introducing CONFIG_SOC_PART_NUMBER_* to
provide a SOC model config
- introducing the 'common' folder to hide all
commonly used configs and files.
- updating west.yml to reflect previous changes in hal
Signed-off-by: Marek Matej <marek.matej@espressif.com>
Remove virtual esp32 board and replace it with the
real word boards:
- esp32_devkitc_wroom
- esp32_devkitc_wrover (with PSRAM option)
Signed-off-by: Marek Matej <marek.matej@espressif.com>
Introduce dtsi files representing the
current portfolio of chips and modules
based on the:
- flash size
- psram size
- gpio count
- certification status
Update the boards dts files according
to which SOC/SIP they are using.
Signed-off-by: Marek Matej <marek.matej@espressif.com>
Introduce dtsi files representing the
current portfolio of chips and modules
based on the followint criteria:
- flash size
- psram size
- gpio count
- certification status
Update the boards dts files according
to which SOC/SIP they are using.
Signed-off-by: Marek Matej <marek.matej@espressif.com>
CPU idle states are not board specific. This patch moves Nuvoton idle
states to the core SoC dts files. Board can always tweak some state
parameters (if needed), but the definition belongs to core SoC dts
files, same as e.g. peripherals.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
CPU idle states are not board specific. This patch moves NXP idle states
to the core SoC dts files. Board can always tweak some state parameters
(if needed), but the definition belongs to core SoC dts files, same as
e.g. peripherals.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
CPU idle states are not board specific. This patch moves Microchip MEC
idle states to the core SoC dts files. Board can always tweak some state
parameters (if needed), but the definition belongs to core SoC dts
files, same as e.g. peripherals.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
CPU idle states are not board specific. This patch moves TI idle
states to the core SoC dts files. Board can always tweak some state
parameters (if needed), but the definition belongs to core SoC dts
files, same as e.g. peripherals.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
