Doing a `GCLK->CTRLA.bit.SWRST = 1` will cause boot chaining to hang.
Setting the CPU clock to run from OSCULP32K during initialization is
all that is needed.
Signed-off-by: Jon Ringle <jringle@gridpoint.com>
Issue an upstream read transaction through uncached memory to flush
out all pending transactions before power down the host domain.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Fixes: #69785
The boards_legacy sub-folder was temporarily introduce in collab-hwm
branch during porting to HWMv2.
This should have been removed before merging collab-hwm to main as it
prevent looking up boards in oot roots.
Removing the temporary sub-folder for HWMv2.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
Clean up early days TF-M development directives which are outdated today.
Factorize remaining CMake instructions in soc.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Replaces inaccurate or wrong vendor prefixes in board and soc
folder names with those from thr vendor prefix file
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Move the Kconfig symbols SOC_ESP32_PROCPU, SOC_ESP32_APPCPU,
SOC_ESP32S3_PROCPU, and SOC_ESP32S3_APPCPU.
The CPU cluster is defined in espessifc/soc.yml and should therefore
be available in the HWMv2 Kconfig.soc tree.
This will allow sysbuild to test for the CPU cluster when targeting
remote board for a build.
Update espressif boards accordingly.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
Interrupts should not be enabled this early in boot time.
Driver initializations expect IRQs not to arrive when
setting up HW.
Remove enabling `MSTATUS.MIE` in `__start`.
It will be enabled when main thread is switched to,
as threads by default start with enabled `MSTATUS.MIE`.
Signed-off-by: Marcin Szymczyk <marcin.szymczyk@nordicsemi.no>
Due to HW issue, VPR needs to keep MSTATUS.MIE enabled during sleep.
Otherwise, interrupts will not wake it up.
Signed-off-by: Marcin Szymczyk <marcin.szymczyk@nordicsemi.no>
MEMC_MCUX_FLEXSPI depends on code relocation being enabled on parts that
XIP from the FlexSPI by default and requires a string describing the RAM
region to relocate code into. Add these Kconfigs to the RW SOC port.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This patch updates the power status register bitfield definitions in the
power management header for the Intel ADSP ACE 2.0 LNL platform.
Modifications include:
- Adjusting the 'ioxpgs' field from 4 bits to 2 bits.
- Adding a 'rsvd11' field with 2 bits to reflect reserved space.
- Changing the 'mlpgs' field from 2 bits to 1 bit.
- Updating the 'rsvd14' field from 1 bit to 2 bits for alignment.
These changes ensure that the power status register bitfields match the
latest hardware specification for the ACE 2.0 LNL SoC, which is crucial
for accurate power domain status monitoring.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
In the interrupt pending routine, only the interrupt status needs to be
cleared at the end of the interrupt routine. There is no need to do a
hardware reset(HALT) to avoid clearing the next transfer interrupt when
the current transfer is completed.
Test: Testing this function does not cause I2C data/clk to get stuck on
the system platform.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Add support for propagating SOC_NRF54LX_DISABLE_FICR_TRIMCNF and
SOC_NRF54LX_SKIP_GLITCHDETECTOR_DISABLE values to nrfx.
Signed-off-by: Magdalena Pastula <magdalena.pastula@nordicsemi.no>
Previous adjustments to hwmv2 lost this Kconfig file.
Test: west build -p always -b it82xx2_evb samples/hello_world
config BOARD_IT82XX2_EVB
select SOC_IT82302_AX
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
When non-primary core is powered down and restart with sequence of:
- PM state set to SOFT_OFF
- once target core is idle, cut power with soc_adsp_halt_cpu()
- power up core again with k_smp_cpu_resume()
The execution will continue from stored DSP core context, but
will hit an assert in z_smp_cpu_mobile() as the PS.INTLEVEL
is zero.
Fix this issue by storing and restoring PS register in this flow.
Link: https://github.com/zephyrproject-rtos/zephyr/issues/70181
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
The core clock of 8ULP's HIFI4 DSP runs at 475.2MHz. As such,
correct the value of `CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC` to
reflect this.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Transition to a low power DMI L1 state should be allowed only after all
pending DMA channels transfers have started.
Signed-off-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
Dependencies of NXP_IMXRT_BOOT_HEADER were set incorrectly for the
RT11xx series part when building a dual core image. The boot header
should be enabled by default for the primary M7 core, and always
disabled when MCUBOOT is used or the M4 core is targeted
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Use `DT_REG_HAS_IDX()` instead of `DT_NODE_EXISTS()` when checking
if for a given nodelabel the base address of the associated node
should be validated, so that the validation is performed only if
the base address is available. This prevents build failures in cases
like the os_mgmt_datetime test where the `rtc` nodelabel is used for
an emulated RTC.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Unlike the remainder of the RT10xx series, the RT1011 SOC requires that
the flash configuration block be placed at an offset of 0x400 bytes,
instead of the start of the flash.
Fixes#70090
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
With the transition to HWMv2, `CONFIG_CPU_HAS_DCACHE` is no
longer selected. This causes issues with Sound Open Firmware
since this configuration allows the usage of DCACHE-related
cache management operations. As such, to fix said issues,
select `CONFIG_CPU_HAS_DCACHE` on all NXP ADSP SOCs.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
Check the driver configuration to disable
the USB Type-C dead battery, only if
- a USB PD system is in place (the UCPD node is enabled)
- or the user does not require USB PHY anyway
Signed-off-by: Francois Ramu <francois.ramu@st.com>
In case the core is not power gated, waiti will restore intlevel. In
this case we lock interruption after it.
In the bug scenario, the host starts streaming and via SOF APIs, keeps a
lock to prevent Zephyr from entering PM_STATE_RUNTIME_IDLE. During the
test case, host removes this block and core0 is allowed to enter IDLE
state.
When core0 enters power gated state, interrrupts are left enabled (so
the core can be woken up when something happens). This leaves a race
where suitably timed interrupt will actually block entry to power gated
state and k_cpu_idle() in power_gate_entry() will return. This is rare,
but happens often enough that the relatively short test plan run on SOF
pull-requests will trigger this case.
Fixes#69807
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The option SOC_NRF54L_GLITCHDET_WORKAROUND is not
needed anymore becuase the glitch detector is already
disabled in the Nordic MDK in the hal_nordic repo.
File path in hal_nordic:
nrfx/mdk/system_nrf54l.c
Signed-off-by: Georgios Vasilakis <georgios.vasilakis@nordicsemi.no>
