Abstract some SPI LL function call for future driver compatibility with
a new SPI peripheral version (introduced with STM32MP1x and STM32H7x
SoC)
Signed-off-by: Yaël Boutreux <yael.boutreux@st.com>
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
This commit solves an issue where the NSS must be set before the
mode on the stm32mp157c_dk2, else LL_SPI_SetMode won't affect the
mode registry.
stm32mp1x (and stm32h7) LL function SPI_Init seems to also define
first the NSS then the mode, unlike other STM32 boards where this
is not specified.
Changing the order shouldn't have bad repercussions on other boards,
ZephyrnSPI driver test has been passed successfully on disco_l475_iot1
board.
Signed-off-by: Yaël Boutreux <yael.boutreux@st.com>
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
SPI NOR devices require that writes be performed within only one page at
a time. There is no such limitation on reads. Remove the code that
forced reads to be performed in 256-byte chunks.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
The code failed to increment the address after completing a partial
write, causing writes that cross a page boundary overwrite at a page
level.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
Add the serial wire JTAG configuration of the stm32f1x family.
Before gpio is initialized, you can choose to turn off the debug pin to
make the used pins available.
Signed-off-by: Findlay Feng <i@fengch.me>
STM32 clock control subsystem allows to configure a different
frequency value for core clock (SYSCLK) and AHB clock (HCLK).
Though, it is HCLK which is used to feed Cortex Systick timer
which is used in zephyr as reference system clock.
If HCLK frequency is configured to a different value from SYSCLK
frequency, whole system is exposed to desynchro between zephyr clock
subsytem and STM32 HW configuration.
To prevent this, and until zephyr clock subsystem is changed to be
aware of this potential configuration, enforce AHB prescaler value
to 1 (which is current default value in use for all STM32 based
boards).
On STM32H7, enforce D1CPRE which fills the same role as ABH precaler.
On STM32MP1, the equivalent setting is done on A7 core, so it is
not exposed to the same issue as long as SYS_CLOCK_HW_CYCLES_PER_SEC
is set with the 'mlhclk_ck' clock frequency value. Update
matching boards documentation.
Fixes#17188
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
With the upcoming riscv64 support, it is best to use "riscv" as the
subdirectory name and common symbols as riscv32 and riscv64 support
code is almost identical. Then later decide whether 32-bit or 64-bit
compilation is wanted.
Redirects for the web documentation are also included.
Then zephyrbot complained about this:
"
New files added that are not covered in CODEOWNERS:
dts/riscv/microsemi-miv.dtsi
dts/riscv/riscv32-fe310.dtsi
Please add one or more entries in the CODEOWNERS file to cover
those files
"
So I assigned them to those who created them. Feel free to readjust
as necessary.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Even one liner if () statement should have braces.
Fixing parameter indentation as well.
Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
Add a new sifive,plic-1.0.0 binding that inherits from the riscv,plic0
binding. The new binding adds a required riscv,ndev property, which
gives the number of external interrupts supported.
Use the new binding for microsemi-miv.dtsi (with a value of 31 for
riscv,ndev, from http://www.actel.com/ipdocs/MiV_RV32IMAF_L1_AHB_HB.pdf)
and riscv32-fe310.dtsi (which already assigns riscv,ndev).
Also remove a spurious riscv,ndev assignment from
riscv32-litex-vexriscv.dtsi.
Also make edtlib and the old scripts/dts/ scripts replace '.' in
compatible strings with '_' when generating identifiers.
Signed-off-by: Ulf Magnusson <Ulf.Magnusson@nordicsemi.no>
This commit fixes following issues in printf formatting used by flash
drivers:
- cast values of type off_t to long to remove warnings generated when
compiling with Newlib.
- use 'z' modifier (as in "%zu") to print values of type size_t
- prefix all hex numbers with '0x'
Signed-off-by: Piotr Mienkowski <piotr.mienkowski@gmail.com>
Split a long line remaining in the driver.
Signed-off-by: Yaël Boutreux <yael.boutreux@st.com>
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Allow the user to use software slave select instead of the
hardware pin, in order to free the related GPIO and avoid
unwanted SS triggering on the hardware pin. The default SS
is still the hardware pin.
Signed-off-by: Yaël Boutreux <yael.boutreux@st.com>
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Fixes#16739. Changed the STM32's SPI MISO/MOSI configurations in order
to reduce the power consumption by approximately 20uA per pin.
According to STM32's Application Notes on GPIO configuration for
low-power consumption, the input pins should be configured with internal
pull-up or pull-down resistor. If a pin is configured as a floating
input, and there is no signal present, the Schmitt trigger randomly
toggles between the logical levels induced by the external noise, thus
increasing the consumption.
Signed-off-by: Ioannis Konstantelias <ikonstadel@gmail.com>
Update the logic in a corner case, when the target comparator value is
one cycle ahead of the counter value.
Experiments have shown, that `set_comparator(cyc + 1);` might be not
enough in that case, and we still may (rarely) miss the interrupt.
This could happen when the counter incremented its value after the `dt`
variable was set. As we should set the comparator value two cycles
ahead to be on the safe side, increment the target comparator value
by 2 instead of 1.
Signed-off-by: Robert Lubos <robert.lubos@nordicsemi.no>
pinmux: Add the relevant definition of the spi3 pin
dts: Fix a bug, spi3 does not have a label
soc: Supplement spi3 related definition
Signed-off-by: Findlay Feng <i@fengch.me>
Add support for virtual UART device that uses Segger RTT channels
for data transfers. Due to the RTT principle, this driver supports
only polling API.
Signed-off-by: Pavel Kral <pavel.kral@omsquare.com>
Add a hidden Kconfig option indicating that a given SoC is equipped
with the IEEE 802.15.4 capable radio so that the corresponding driver
configuration can depend on it.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
The i2c5 instance are used on arduino connector of
stm32mp157c-dk2.
Signed-off-by: Christophe Priouzeau <christophe.priouzeau@linaro.org>
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@linaro.org>
Add support of I2C. Add I2C5 configuration for the
arduino connector support.
Signed-off-by: Christophe Priouzeau <christophe.priouzeau@linaro.org>
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@linaro.org>
We generated a define for each instance to convey its existance of the
form:
#define DT_<COMPAT>_<INSTANCE> 1
However we renamed all other instance defines to be of the form
DT_INST_<INSTANCE>_<FOO>. To make things consistent we now generate a
define of the form:
#define DT_INST_<INSTANCE>_<COMPAT> 1
We also now deprecate the DT_<COMPAT>_<INSTANCE> form and fixup all uses
to use the new form.
Fixes: #17650
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This board and SoC was discontinued some time ago and is currently not
maintained in the zephyr tree.
Remove all associated configurations and variants from the tree.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Up to now, the only SOC that was supported in the STM32L496 series was
STM32L496XG with flash of 1MB. With the recent support of STM32L496XE,
this implementation is not correct. This patch adds support for the
other SOCs that come with flashes of 512KB and 256KB.
Signed-off-by: Ioannis Konstantelias <ikonstadel@gmail.com>
Make use of the new flag introduced in nrfx v1.7.2 that suspends
transfers, in order to properly handle scattered I2C transactions,
especially to perform i2c_burst_write() in the way expected by
display drivers, i.e. as a continuous transaction on the bus,
without the repeated START between its two parts.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Implement a CAN shell. With this shell you can send messages,
attach and tetach filters.
Messages that match the attached filters are printed to the shell.
Signed-off-by: Alexander Wachter <alexander.wachter@student.tugraz.at>
HSEM_CR_COREID_CURRENT was used as process number parameter in
LL_HSEM_ReleaseLock function. While this is working, this
define should not be used in this context.
Also, process number parameter is actually proposed in case of HSEM
use in inter-process context but is not required for inter-core
resource lock. Replace HSEM_CR_COREID_CURRENT with 0.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add eSPI Microchip XEC driver
Include support for peripheral & virtual wires (channel 0-1)
OOB and flash support can be added in the future
Fix compilation error in pinmux driver
Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
Sometimes i2c operation does not return in a while loop.
Fix this by adding timeout to the i2c driver.
Fixes: #12261
Signed-off-by: Kwon Tae-young <tykwon@m2i.co.kr>
Add a kernel timer driver for the MEC1501 32KHz RTOS timer.
This timer is a count down 32-bit counter clocked at a fixed
32768 Hz. It features one-shot, auto-reload, and halt count down
while the Cortex-M is halted by JTAG/SWD. This driver is based
on the new Intel local APIC driver. The driver was tuned for
accuracy at small sleep values. Added a work-around for RTOS
timer restart issue. RTOS timer driver requires board ticks per
second to be 32768 if tickless operation is configured.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
The previous code limited the length of a write to the size of a page,
but did not check whether the starting position was far enough into the
page that the write would still cross a page boundary.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
This was always intended to be a bytestring rather than an array, but
full support was missing. Since that has been addressed switch it to
the preferred format.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
The driver historically used the erase block size (64 KiBy) as the page
size. There are other viable "sector" sizes, and for some applications
this one may be too large. Allow the application to specify the desired
flash page size.
Signed-off-by: Peter A. Bigot <pab@pabigot.com>
