Fix register bit field when clock source is MSI
on the stm32L0x or stm32L1x mcus
Use RCC_CR_MSIRGSEL bit field instead of not soc stm32wbx serie
That bit of the RCC CR is common to several stm32 mcus
Signed-off-by: Francois Ramu <francois.ramu@st.com>
The temperature sensor used in the clock_control driver requires
multithreading, but this is not compatible with mcuboot builds with
multithreading disabled.
Fixes#41597.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
According to Kconfig guidelines, boolean prompts must not start with
"Enable...". The following command has been used to automate the changes
in this patch:
sed -i "s/bool \"[Ee]nables\? \(\w\)/bool \"\U\1/g" **/Kconfig*
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Shims for nrfx drivers should only connect the related IRQ handlers,
they should not enable the IRQs, as this could lead to a situation
where the interrupt handler is called before the driver had a chance
to properly initialize the peripheral and install the provided event
handler. nrfx drivers will enable the interrupts appropriately on
their own by calling the NRFX_IRQ_ENABLE macro which is implemented
in nrfx_glue.h as a call to irq_enable().
This commit fixes the above issue spotted in the following shims:
- dmic_nrfx_pdm
- clock_control_nrf
- i2s_nrfx
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Instead of reading registers query the info on sysclock configuration
from existing configuration symbols.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Rework clock start up functions in order to allow configuration
and enabling of individual clocks.
This way, each clock defined with a "okay" status will be enabled
even if not part of the sysclock clock tree.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Add STM32_FOO_ENABLED and STM32_FOO_FREQ to STM32 fixed clocks:
HSI, HSE, MSI(S), CSI, LSI, LSE..
Replace STM32_LSE_CLOCK by STM32_LSE_FREQ and when possible
replace by new STM32_LSE_ENABLED when making sense.
Fix STM32_PLL3_FOO_ENABLE to STM32_PLL3_FOO_ENABLED
Additionally, add STM32_PLL_FOO_ENABLED definitions.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
PLL3 setting should also be protected CFG_HW_RCC_SEMID.
Move semaphore unlock after we're done with PLL3.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
STM32H7B3 supports max SYSCLK and AHB clock frequencies of 280 MHz,
and max APB frequency of 140 MHz
Signed-off-by: Tomislav Milkovic <tomislav.milkovic95@gmail.com>
An optional reference to the temperature sensor can be obtained at
compile time, update implementation.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
This commit sets the power down bit of the module SDP, UART3, UART4,
and I3C by default. The module's driver should take the responsibility
to clear it to turn on the power. It helps reduce the power consumption
when an application doesn't use these modules.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
This corrects the following:
1. The priority of type cast is lower than member access. So don't need
the redundant parentheses.
2. The macro should be added to the parentheses.
Signed-off-by: Wealian Liao <WHLIAO@nuvoton.com>
Build shows warning due to incompatible
CPU vendor name. This fixes it and applies
necessary changes in files.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
1. Update to add support for Flexcomm8-13.
2. Fix the clock control driver, the enclosing #define
was incorrect.
3. Identify HS_SPI port using the appropriate Register
define
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Stop using redundant DEV_DATA/DEV_CFG macros and use dev->data and
dev->config instead.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Recent changes in this function made the code now compatible
with the use of LL API to perform this configuration.
Use it to simplify the driver.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
Voltage scaling computation should be done in multiple cases.
Add a function that takes into account all cases.
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
STM32H7 has different power supply modes but now Zephyr supports just LDO
and direct SMPS. This commit introduses POWER_SUPPLY_CHOICE configuration
parameter and add support for missed power supply modes.
Signed-off-by: Gennady Kovalev <gik@bigur.com>
Fixes#40730.
DMA controller is enabled and tested for cortex M7 core. The M7 core was
tested on the loop and channel link transfer tests.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
the RT685 contains an additional flexcomm peripheral, that supports
only I2C. This commit adds this peripheral to the device tree,
and enables pins and clocks for flexcomm15.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
MCUX PWM driver used hardcoded clock source. update driver to use clock
bindings to determine PWM peripheral clock frequency.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
In case of MSIS selected as system clock source it is necessary
to set Voltage scaling (VOS) when freqency is greater than 24MHz
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
When MSI trimming values where set to 0,
and MSIS is used as system core clock and MSI > 4 MHz,
it causes uart to fail.
There is no need to set thoses trimming values.
So keep the default reset value. (keep ST Factory calibration)
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
Because on stm32u5 MSIS is the default clock after reset,
changing MSIS range means immediate frequency change.
Thus it is important to do it after flash latency change
in case of higher new frequency.
Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
This joins all clock control handling to same source
by using hal clock functions. It also brings ESP32C3
clock support.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
This commit is fixing the error on clock control for the AHB3
in the stm32_clock_control_off function.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
