Add support for reclocking flexspi in ccm_rev2 driver. Clock update
functions are provided for the RT11xx.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add support for reclocking the FlexSPI on NXP iMX RT10XX. This
functionality requires an SOC specific clock function to set
the clock rate, since the FlexSPI must be reset directly
before applying the new clock frequency.
Note that all clock constants are defined in this commit, since the
memc flexspi driver now depends on a clock node being present.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Consistently use `zephyr_library*` cmake functions for all nRF Series
and set the Cortex-M linker script in a common place for all of them.
Remove no longer needed include directories.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
In nRF54L15 FICR can be accessed also from non-secure code,
so it does not have NRF_FICR_S defined.
Signed-off-by: Magdalena Pastula <magdalena.pastula@nordicsemi.no>
NRF_RTC_TIMER will not be a default timer in the next
version of Nordic timer. It should be soc selection specific.
Signed-off-by: Witold Lukasik <witold.lukasik@nordicsemi.no>
The RA_PINCFG macro is used to generate a value that can be written
directly to the pin function select register. In addition to the pin
function this value also contains port and pin number information,
located in bit fields that are unused by the register. The bit field
used to store the port information consists of 3-bits. However, a typo in
the mask definition limited the field to two bits meaning only ports 0-3
could be configured. This patch resolves the issue, allowing ports 0-7 to
be configured. If the port is greater than 7 another field (port4) is used
to store an additional bit (allowing an additional 8 ports to be
supported). However, use of this field has not yet been implemented.
Signed-off-by: Ian Morris <ian.d.morris@outlook.com>
Adds CAN drivers for XMC4xxx SoCs.
XMC4xxx has multiple CAN nodes. The nodes share a common clock and
a message object pool.
The CAN nodes do not have a loopback mode. Instead there is an
internal bus which can be used to exchange messages between
nodes on the SoC. For this reason tests/samples which rely on the
loopback feature have been disabled.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
SOCFPGA_SYSMGR_REG_BASE base address now read from Device tree
This commit changes the way the SOCFPGA_SYSMGR_REG_BASE base address is
determined. Previously, the address was hard-coded in the system_manager
source file. This commit changes the code to read the address from the
Device tree. This makes the code more flexible and allows the base
address to be different for different boards.
Signed-off-by: Navinkumar Balabakthan <navinkumar.balabakthan@intel.com>
In pm_state_set we can't just call k_cpu_idle() because
this will clear out PS.INTLEVEL. Use k_cpu_atomic_idle instead
since Zephyr's expect interruptions to be locked after pm_state_set.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
We are arbitrarily setting a value to PS after power gates and
losing valid information like OWB, CALLINC and INTLEVEL.
We need to properly save/restore them to avoid possible wrong behavior.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
ROM configures the ISP boot pins as gpio to determine what boot mode to
be in. But some ROM revisions have a bug where they do not restore the
reset state of these pins before booting application. This can cause
power leakage on these pins and is not an intended configuration from
Zephyr user/board point of view, so restore the reset state as part of
early SOC init (disable the pins). Configuration of pins should be
left up to app/board devicetree.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
The OpenTitan PLIC has support for up to 255 interrupt vectors, so
set it to that. Previously was set to number of IRQs used.
Signed-off-by: Tyler Ng <tkng@rivosinc.com>
There is default 15K-ohm pull-down for USB controller.
To disable the default pull-down to avoid signal contention in GPIO mode.
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
At chip startup, jtag pins are configured by default to enable
debug.
This configuration adds consumption and when using PM profile,
we can save ~40uA by resetting this configuration and setting pins
to analog mode.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Only when CONFIG_MP_MAX_NUM_CPUS > 1, then .bss is put in
uncached region. Otherwise, .bss is in cached region.
So the assertion that g_key_read_holder must be in uncached
region must take into account how many CPUs are enabled on
build.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Commit 3b99fb1b4a ("xtensa: do not imply atomic ops kconfig") removed
ATOMIC_OPERATIONS_ARCH at xtensa arch level. This triggers a bug in
intel_adsp cavs builds with XCC compiler as
CONFIG_ATOMIC_OPERATIONS_BUILTIN is not defined but neither is
CONFIG_ATOMIC_OPERATIONS_ARCH anymore, resulting in failed builds.
Fix the XCC build by defining CONFIG_ATOMIC_OPERATIONS_ARCH at
soc level.
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
The STM32G0 soc has 2 CAN controllers. The 2nd on was not working
with zephyr yet as both controllers shares the same IRQ. Recently, the
shared irq system was integrated on now, both can controllers can work
on this chip. Shared interrupts must be enabled only if both can
controllers are enabled.
Signed-off-by: Adrien MARTIN <adrienmar@kickmaker.net>
This allows to link code and data blocks, e.g. the vector table, into
tightly coupled memory using `zephyr_linker_sources`.
Signed-off-by: Greter Raffael <rgreter@baumer.com>
When set, this GPIO controller has pins associated with the
keyboard controller. In this case the reg_gpcr property is
overloaded and used to write the keyboard GCTRL register
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Updated the files present in device_init, hfxo_manager, power_manager
and sleeptimer folder as per latest version of gecko_sdk.
Added SL_DEVICE_INIT_HFXO_PRECISION in sl_device_init_hfxo_config.
Signed-off-by: Sateesh Kotapati <sateesh.kotapati@silabs.com>
With the introduction of the SAI and EDMA drivers, there's
no longer a need to map the MMIOs using the mmu_regions.c
method since this is taken care of by the drivers via
device_map(). As such, remove entries for EDMA and SAI from
mmu_regions.c.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
It looks like all SoCs in tree check if an exception comes from an IRQ
the same way, so let's provide a common logic by default, still
customizable if the SoC selects RISCV_SOC_ISR_CHECK.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
use CONFIG_SOC_INTEL_ACE15_MTPM instead of CONFIG_ACE_VERSION_1_5.
CONFIG_ACE_VERSION_1_5 leaked from SOF.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Add functions to Atmel SAM SoC PMC API. This is an effort to hide
most of the internal registers used in different SAM families.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
The clock z_arm_platform_init hangs switching between clocks when using
MCUboot. This fixes the issue using the 8MHz internal clock as gclk_main
source when configuring PLL/DFLL.
Fixes: #67220
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
The HAS_SPI_DW Kconfig is rather unncessary. If the synopsys designware
spi is to be included. It should come from the devicetree.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
Some definitions were only used in soc.c, there's no need to expose them
in a public header like soc.h.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
<soc.h> is needed to pull some APIs defined in soc.h.
<fsl_device_registers.h> is needed to access EVENT0/1 addresses.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
