2 commits

Author	SHA1	Message	Date
Filip Kokosinski	806c95163a	dts/riscv: add missing riscv,isa fields and modify existing ones ... This commit adds/modifies `riscv,isa` strings using the following rules: * the ISA string is lowercase * multi-letter extensions are preceded with the underscore mark * if an extension is implied by another one, it is not specified - e.g. the D extension implies the F extension, so writing `rv32ifd` is redundant Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>	2023-09-14 14:34:34 +02:00
Tim Lin	e8366689d1	ITE: dts: cpu/yaml: fix the name of compatible ... This name should be the same as cpus node in dtsi. After the power policy is added, the cpu-power-states in the CPU properties can be used. Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>	2021-10-07 06:09:45 -05:00

Renamed from dts/bindings/cpu/riscv,it8xxx2.yaml (Browse further)