The purpose of this separation is to avoid conflict initializing
gpio-keys because button 0 and joystick up have a shared interrupt
source. Joystick is now configured using polling mode option.
Signed-off-by: Joel Guittet <joelguittet@gmail.com>
This allows to run tests & examples on the physical board with:
```
west twister -p mps2_an521 --device-testing --device-serial /dev/ttyUSB0
```
Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
Create a folder for RZ Renesas range device tree to follow how it's
done for other renesas ranges.
It will also help to better delimit areas to maintain.
Signed-off-by: Aymeric Aillet <aymeric.aillet@iot.bzh>
- Remove hadcoded cc2538-bsl.py path
- Use cc1352-flasher program instead
- Add docs about how to install the program
Signed-off-by: Ayush Singh <ayushdevel1325@gmail.com>
This commits makes it possible to use the onboard bluetooth
module (STM32WB5MMG) with existing zephyr bluetooth samples.
Note that there was no hardware flow control wiring
available on the board, which is why it has been disabled
in the both main board and BLE module Device Tree. As the
board doesn't support HW flow control, users must set
CONFIG_BT_HCI_ACL_FLOW_CONTROL=n in project files.
Signed-off-by: Javad Rahimipetroudi <javad.rahimipetroudi@mind.be>
This patch introduces the Bluetooth Low Energy (BLE) feature to the board.
The board utilizes the STM32WB5MMG as the BLE module. However, As there
was no BLE controller available for this module. Therefore, a board
support package has been added to enable the STM32WB5MMG module to act as
a BLE controller. This is achieved by running Zephyr's hci_uart example on
the STM32WB5MMG module which enables communication with the main
microcontroller over the H:4 HCI transport protocol. So, users must first
build the BLE controller for the BLE module and upload it via on board
ST-Link,then they can uses Zephyr Bluetooth demos on the development board
Note that there was no hardware flow control wiring available on the
board, which is why it has been disabled in the both main board and BLE
module Device Tree.
Signed-off-by: Javad Rahimipetroudi <javad.rahimipetroudi@mind.be>
OpenOCD can now be used to flash and debug nucleo_wba52cg.
However it required use of STMicroelectronics OpenOCD fork.
Add instructions on how to use it.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
This reverts commit 6a3612666e
"boards: mps2_an385: Exclude platform from networking tests"
This would have found the issue described in #67762 where a
network test was failing because of wrong section placement.
All the simulated environments (qemu_x86 and native_sim) used
in network testing missed this problem, but could have easily
found if network tests would have been run in mps2_an385.
Signed-off-by: Jukka Rissanen <jukka.rissanen@nordicsemi.no>
Define the pinctrl-based pin controller instance
for the Mercury XU board and remove the old implementation
Signed-off-by: Jan Bylicki <jbylicki@antmicro.com>
Setting an extremely low value by default on two boards doesn't seem
like the right thing to do. The defaults were added with the v1 logging
subsystem in https://github.com/zephyrproject-rtos/zephyr/pull/8023.
Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au>
The nucleo_g0b1re board is based on stm32g0 that supports 2 can
controllers. This commit adds support for the second can controller.
Add also can label in yml board file.
Signed-off-by: Adrien MARTIN <adrienmar@kickmaker.net>
This patch add the basic board support for the
STM32WB5MM-DK Discovery Kit. At the moment only
debug UART Debug is ported. Other peripherals will be added
in the following patches.
Signed-off-by: Javad Rahimipetroudi <javad.rahimipetroudi@mind.be>
In order to build a BLE application nucleo_wba55cg fecthing controller
blobs is required. Document the command.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
According to the documentation and pinctrl file, sercom0 tx should
be available on PA10C/SERCOM_PAD[2]. However, and somewhat confusingly,
txpo 2 meant SERCOM_PAD[0] with RTS/CTS flow control.
Changing this to txpo 1 uses SERCOM_PAD[2], which allows sercom0
to work as documented.
Signed-off-by: Tom Rothamel <tom@rothamel.us>
Changes:
* Fixed typo in the PWM channel number (32 -> 3)
* Added a prescaler to make the board compatible
with the blinky_pwm sample
Output of the sample before the fix:
PWM-based blinky
Calibrating for channel 32...
[00:00:00.010,000] <err> pwm_stm32: Invalid channel (32)
[00:00:00.016,000] <err> pwm_stm32: Invalid channel (32)
[00:00:00.022,000] <err> pwm_stm32: Invalid channel (32)
[00:00:00.028,000] <err> pwm_stm32: Invalid channel (32)
[00:00:00.034,000] <err> pwm_stm32: Invalid channel (32)
[00:00:00.040,000] <err> pwm_stm32: Invalid channel (32)
Error: PWM device does not support a period at least 31250000
After the fix:
PWM-based blinky
Calibrating for channel 3...
Done calibrating; maximum/minimum periods 1000000000/7812500 nsec
Presence of PWM signal after the fix
has been confirmed using a logic analyzer.
Signed-off-by: Maksim Salau <maksim.salau@gmail.com>
Switch the default MCUBoot FW Update mode from Swap & Scratch
to more preferable Swap & Move for the rest of NXP MCUs.
Other NXP MCU platforms have been already switched.
Delete the scratch partition. Save RAM & ROM.
Slot 0 has one additional sector, for use with
the swap move algorithm.
Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
Update generation comment for NXP board pin control files, to point
users to the current pin control scripting files in NXP's HAL. Note that
these files have not been regenerated- the script name simply has
changed, so update these references to avoid confusion.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Using the recently added WS2812 PIO driver, this enables the LED on the
QT PY to work with the built in RGB LED examples.
Signed-off-by: Ian Wakely <raveious.irw@gmail.com>
Update source lib and include path for TF-M interface files.
Signed-off-by: Joakim Andersson <joakim.andersson@nordicsemi.no>
Signed-off-by: Markus Swarowsky <markus.swarowsky@nordicsemi.no>
The place where TF-M places its non-secure api header files has changed
Therefore changing it for for all applications that use it.
Signed-off-by: Markus Swarowsky <markus.swarowsky@nordicsemi.no>
Enable L/R channel pair for DMIC0 on the RT595 EVK. The RT595 EVK has a
pair of MEMS microphones wired to PDM channel 0 and 1, so these channels
are configured with appropriate gain and filter settings for the MEMS
microphones.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Co-authored-by: Yves Vandervennet <yves.vandervennet@nxp.com>
This update stm32h747i_disco board display config to use ltdc frame
buffer config feature.
For lvgl, by default ltdc frame buffer number set to 0.
Signed-off-by: HaiLong Yang <hailong.yang@brainco.cn>
Add flash partitions required to use the board with MCUboot.
Also fix the chosen zephyr,code-partition devicetree node and point it
to slot0_partition.
Signed-off-by: Martin Jäger <martin@libre.solar>
Add flash partitions required to use the board with MCUboot.
Also fix the chosen zephyr,code-partition devicetree node and point it
to slot0_partition.
Signed-off-by: Martin Jäger <martin@libre.solar>
Add the possibility to flash stm32h747i_disco board using west
STM32CubeProgrammer runner, for both cores.
Signed-off-by: Abderrahmane Jarmouni <abderrahmane.jarmouni-ext@st.com>
CONFIG_STM32_LPTIM_CLOCK_LSE definition is now defined directly from
device tree, remove from boards definition.
Solving systematic warning about CONFIG_STM32_LPTIM_CLOCK_LSE being
selected with unsatisfied dependencies.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Since the pins of bt-spi instance are wired internally in the chip, it will
make sense to move the definition to soc dts so no need for every board
using the chip to redefine the same.
Signed-off-by: Aaron Ye <aye@ambiq.com>
Adds the device trees, Kconfig, and documentation files.
The following features have been confirmed working on hardware:
* LED
* Button
* UART
Signed-off-by: Charles Dias <charlesdias.cd@outlook.com>
Power profiles enable the app to dynamically switch modes and support
DVFS. These profiles leverage the PCA9420 PMIC to change the VDDCORE
voltage, and optimize power consumption. Two runtime profiles are
provided for the application:
* main_clk sourced from FRO192M, VDDCORE at 0.9 V
* main_clk sourced from FRO96M, VDDCORE at 0.8 V
Both profiles use the FRO, and the FRO is retrimmed with the target
frequency when switching profiles.
Signed-off-by: Derek Snell <derek.snell@nxp.com>
Due to board name change (JUNO -> SBC-3.5-PX30), it is necessary to
update board names, links and references in files and documentation.
Signed-off-by: Ettore Chimenti <ek5.chimenti@gmail.com>
Add support for specifying the domain/kernel clock along with a common
clock divider for the STM32H7 CAN controller driver via devicetree.
Previously, the driver only supported using the PLL1_Q clock for
domain/kernel clock, but now the driver defaults to the HSE clock, which is
the chip default. Update existing boards to continue to use the PLL1_Q
clock.
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
