Commit graph

89576 commits

Author SHA1 Message Date
Jukka Rissanen aeb1e41c22 doc: net: Add network configuration guide
Add a simple document describing various network related
configuration options and how they affect the available
resources in the system.

Signed-off-by: Jukka Rissanen <jukka.rissanen@nordicsemi.no>
2024-01-11 10:26:47 -05:00
Jukka Rissanen b8708ee781 net: tcp: Fix the CONFIG_NET_TCP_RETRY_COUNT help text
The help text was incorrect, we return -ETIMEDOUT instead
of -ECONNRESET when retransmission timeout occurs.

Signed-off-by: Jukka Rissanen <jukka.rissanen@nordicsemi.no>
2024-01-11 10:26:47 -05:00
Guennadi Liakhovetski aee2d1a677 llext: provide an example of tristate Kconfig option
Add a tristate Kconfig option to the llext hello-world twister test.

Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
2024-01-11 10:26:04 -05:00
Guennadi Liakhovetski b53a792ff0 llext: enable tristate Kconfig options
kconfiglib.py has a hard dependency on CONFIG_MODULES to support 'm'
values for tristate Kconfig options. It's a logical companion for
but can also be used with other configurations.

Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
2024-01-11 10:26:04 -05:00
Bjarki Arge Andreasen 7d7f7aaf03 tests: subsys: modem: cmux: Update resync unit test
Update the unit test to expect the new simplified resync
behavior, and validate that new resync is working.

Signed-off-by: Bjarki Arge Andreasen <bjarki@arge-andreasen.me>
2024-01-11 13:53:25 +01:00
Bjarki Arge Andreasen 3debfc8c8d modem: cmux: Simplify resync mechanism
Some modems don't start sending resync flags as described in
3G TS 27.010 V2.0.0 5.2.5, which results in the CMUX being
stuck in resync mode for said modems.

This patch simplifies the resync mechanism to simply drop
invalid frames, and wait for atleast two consequtive frame
flags (stop+start).

Signed-off-by: Bjarki Arge Andreasen <bjarki@arge-andreasen.me>
2024-01-11 13:53:25 +01:00
Brian Juel Folkmann 06b57926a2 drivers: adc: stm32: Fix race condition with internal channels
When using one of the internal channels (die_temp, vbat, vref) the
channels are enabled in the individual drivers and disabled again
whenever an adc conversion is complete.

This creates a race condition if the ADC is used from multiple threads.

This commit moves the disabling of the channels to the individual
drivers.

Signed-off-by: Brian Juel Folkmann <bju@trackunit.com>
2024-01-11 13:53:17 +01:00
Yong Cong Sin 768ed26010 doc: posix: signal: fix sigsuspend typo
The `sigsuspend` is currently `igsuspend`, fix that.

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
2024-01-11 07:49:26 -05:00
Yong Cong Sin f82b64504c doc: posix: signal: mark sigprocmask as supported
`sigprocmask()` is now implemented, mark it so.

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
2024-01-11 07:49:26 -05:00
Yong Cong Sin b42e362fa8 tests: posix: pthread: add test for sigprocmask()
Refactor the existing `pthread_sigmask` test function to
get its function-under-test via arg and test `sigprocmask` with
that.

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
2024-01-11 07:49:26 -05:00
Yong Cong Sin 73da1e80f4 posix: signal: implement sigprocmask()
Implement `sigprocmask()` by simply redirecting call to the
`pthread_sigmask()` as they are identical.

Signed-off-by: Yong Cong Sin <ycsin@meta.com>
2024-01-11 07:49:26 -05:00
Henrik Brix Andersen 735c9e23ec boards: arm: nucleo_g474re: list FDCAN1 as supported in the docs
List FDCAN1 as supported in the board documentation.

Fixes: #67087

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2024-01-11 12:52:00 +01:00
Henrik Brix Andersen fcef0607ca boards: arm: nucleo_g0b1re: list FDCAN1 as supported in the docs
List FDCAN1 as supported in the board documentation.

Fixes: #67087

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2024-01-11 12:52:00 +01:00
Ettore Chimenti 3557bfeb60 boards: stm32f3_seco_d23: update name and refs
Due to board name change (JUNO -> SBC-3.5-PX30), it is necessary to
update board names, links and references in files and documentation.

Signed-off-by: Ettore Chimenti <ek5.chimenti@gmail.com>
2024-01-11 11:17:18 +00:00
Flavio Ceolin 8356ec21e5 xtensa: mmu: Fix mmu initialization
The constant used to calculate TLB entries for the way six was wrong
and causing an integer overflow. Consequently only the first 512MB where
being unmapped from the TLB.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2024-01-11 10:05:22 +01:00
Tomasz Leman 1c0c900cbb intel_adsp: ace15: Enhance HST domain power-down sequence
This patch enhances the power-down sequence for the HOST (HST) domain
within the Intel ADSP ACE 1.5 architecture. It introduces a check to
ensure that a specific condition, represented by a magic key value, is
met before disabling the HST domain. This additional verification step
ensures that the HST domain is only powered down when it is safe to do
so, thereby maintaining the stability and reliability of the system.

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
2024-01-11 10:05:12 +01:00
Tomasz Leman c3a6274bf5 intel_adsp: ace: power: Prevent HST domain power gating
This patch introduces power management for the HOST (HST) domain within
the Intel ADSP ACE IP. It adds macros to access the node identifier and
device pointer for the HST power domain and integrates power management
calls into the system initialization and power state transition
functions.

The patch ensures that power gating of the HST domain is prevented when
the primary core of the audio DSP is active. Preventing power gating is
crucial for maintaining the functionality of the HST domain while the
primary DSP core is performing critical tasks.

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
2024-01-11 10:05:12 +01:00
Peter Mitsis 9852e8e15b tests: Add thread suspend-resume SMP stress test
Adds a test to stress k_thread_suspend() and k_thread_resume() on
an SMP system. The test should take about 30 seconds.

Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
2024-01-11 10:05:02 +01:00
Jonathan Rico 1e6ff5ff05 Bluetooth: L2CAP: separate BR/EDR and LE internal headers
Extract BR/EDR definitions from `l2cap_internal.c` into its own headers:
one for the interface with l2cap.c and one for the rest of the BR/EDR
stack.

Signed-off-by: Jonathan Rico <jonathan.rico@nordicsemi.no>
2024-01-11 10:04:53 +01:00
Jonathan Rico 19da13313d Bluetooth: L2CAP: remove usage of bt_l2cap_send_cb by BR/EDR
Isolates BR/EDR's l2cap use from LE (most of l2cap.c).

Why? Because I'm refactoring l2cap.c and don't want to accidentally
break BR/EDR support, as there are very few tests in CI.

This way, once `bt_l2cap_chan_send` hands control to l2cap_br.c, it will
not call back into l2cap.c, it will instead be a parallel layer going
directly to conn.c.

Signed-off-by: Jonathan Rico <jonathan.rico@nordicsemi.no>
2024-01-11 10:04:53 +01:00
Gerard Marull-Paretas 9e5e8e8c40 doc: extensions: zephyr-domain: make Breathe inserts optional
So that external users of the domain only interested in e.g. referencing
roles, can skip tweaks made to Breathe's directives.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-11 10:04:44 +01:00
Gerard Marull-Paretas 9f4a7ba0f5 doc: extensions: zephyr-domain: fix object descriptions
Zephyr's domain code-sample object description was incorrectly yielded,
making Sphinx inventory (objects.inv) unusable on other projects that
need to use the domain via Intersphinx.

Ref. https://www.sphinx-doc.org/en/master/extdev/domainapi.html

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-11 10:04:44 +01:00
Lucas Tamborrino 2ca4ed205f tests: pwm: esp32s3: add internal loopback
Add internal loopback for testing purposes

Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
2024-01-11 10:04:34 +01:00
Lucas Tamborrino 76997374c3 tests: pwm: esp32: add internal loopback
Add internal loopback for testing purposes and
change wroom for wrover, which is default board
for testing.

Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
2024-01-11 10:04:34 +01:00
Mykola Kvach bc90724de4 drivers: serial: uart_rcar: fix reading of SCFRDR register
Fix the read size of the SCFRDR register, which has an 8-bit size
for both Gen3 and Gen4 boards.

Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
2024-01-11 10:04:27 +01:00
Jun Lin 833495675a test: spi_loopback: add npcx evbs to the spi_loopback test suite
This commits adds the npcx4/npcx9/npcx7 evaluation boards to the
spi_loopback test suite.

Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
2024-01-11 10:04:21 +01:00
Jun Lin a897b8a09c drivers: spi: npcx: add driver for the SPI peripheral
This commit adds the driver support for the NPCX SPI peripheral.

Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
2024-01-11 10:04:21 +01:00
Jacob Siverskog 0b74aa0831 manifest: bump hal_nxp revision
this revision contains an usb fix that allows
tests/subsys/usb/device/usb.device to pass on lpcxpresso55s69_cpu0.

see https://github.com/zephyrproject-rtos/hal_nxp/pull/315 for more
information.

Signed-off-by: Jacob Siverskog <jacob@teenage.engineering>
2024-01-11 10:04:13 +01:00
Bryan Zhu aac9b66185 west.yml: hal_ambiq: Update stimer HAL
Update stimer HAL from latested AmbiqSuite.

Signed-off-by: Bryan Zhu <bzhu@ambiq.com>
2024-01-11 10:03:58 +01:00
Chaitanya Tata 918e08fda8 wifi: shell: Add a shell command to list stations
In AP mode maintain the database of connected stations based on the
Wi-Fi management events and dump the list.

Signed-off-by: Chaitanya Tata <Chaitanya.Tata@nordicsemi.no>
2024-01-11 10:03:02 +01:00
Chaitanya Tata 725c13bafb wifi: ap: Add client side events
These are helpful to track clients being added and deleted.
Applications can actions based on these events.

Signed-off-by: Chaitanya Tata <Chaitanya.Tata@nordicsemi.no>
2024-01-11 10:03:02 +01:00
Chaitanya Tata 2703955aee wifi: ap: Add status events
These events communicate the status of AP mode operations (enable or
disable) with few pre-defined enumerations.

Signed-off-by: Chaitanya Tata <Chaitanya.Tata@nordicsemi.no>
2024-01-11 10:03:02 +01:00
Chaitanya Tata 09e1ed039a wifi: Fix duplication
Use a common set of events and then add specific ones as per the
configuration.

Signed-off-by: Chaitanya Tata <Chaitanya.Tata@nordicsemi.no>
2024-01-11 10:03:02 +01:00
Laurentiu Mihalcea 265554b873 drivers: dai: sai: Add fix for i.MX93 SAI errata 051421
ERRATA 051421 states that if the SAI is FSYNC/BCLK master,
one of the directions is SYNC with the other, and the
ASYNC direction has the BYP bit toggled, the SYNC direction's
BCLK won't be generated properly.

This commit fixes this issue by enabling BCI for the SYNC
direction. What this does is it makes the SYNC direction use
the BCLK from the ASYNC direction's pad, which, if the BYP
bit is toggled, will be the undivided MCLK. Without this fix,
the SYNC direction will use the ASYNC direction's BCLK obtained
by dividing the MCLK via the following formula: MCLK / ((DIV + 1) * 2).
This is wrong because the ASYNC direction will use an undivided
MCLK while the SYNC direction will use a divided MCLK.

Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
2024-01-11 10:02:50 +01:00
Laurentiu Mihalcea 0db2d17b48 drivers: dai: sai: Add support for all SYNC modes
With the introduction of the "rx_sync_mode" and "tx_sync_mode"
properties, the user may choose which synchronization mode the
SAI should use. To support this, the code had to be changed a
bit such that the software reset and the disable operations
work on all synchronization modes.

What this commit does, is it changes the software reset and
disable sequences such that they work with any of the
supported synchronization modes. Also, the syncMode field
of sai_transceiver_t structure is set to the value passed
from the DTS during sai_config_set().

Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
2024-01-11 10:02:50 +01:00
Laurentiu Mihalcea 6127535b1d drivers: dai: sai: Introduce the rx_sync_mode/tx_sync_mode properties
In preparation for supporting all synchronization modes, this
commit introduces the rx_sync_mode/tx_sync_mode DTS properties.
Using these, the user will be able to specify which synchronization
mode the SAI should use.

At the moment, the driver does nothing with the values from
said properties but still checks if their values are sane
(i.e: it checks if the directions are both in SYNC mode which
is forbidden). By default, if "rx_sync_mode" or "tx_sync_mode"
is not specified, the direction will be set to ASYNC mode.
As such, below one may find a couple of valid examples
depicting this idea:

	tx_sync_mode = <0>;
	rx_sync_mode = <0>;

is the same as not specifying any of the properties,

	tx_sync_mode = <1>;
	rx_sync_mode = <0>;

is the same as:

	tx_sync_mode = <1>;

Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
2024-01-11 10:02:50 +01:00
Henrik Brix Andersen d7873e25fd boards: arm: stm32h735g_disco: enable CAN suppport
Enable support for FDCAN1, FDCAN2, and FDCAN3 on the stm32h735g_disco
board.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2024-01-10 20:59:55 -05:00
Henrik Brix Andersen 1fa11bd038 doc: release: migration guide: 3.6: add note on stm32h7 CAN domain clk
Add a note describing the new default for the STM32H7 FDCAN CAN controller
domain/kernel clock and how to override it.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2024-01-10 20:59:55 -05:00
Henrik Brix Andersen bc69500b0e drivers: can: stm32h7: fdcan: add support for domain clock and divider
Add support for specifying the domain/kernel clock along with a common
clock divider for the STM32H7 CAN controller driver via devicetree.

Previously, the driver only supported using the PLL1_Q clock for
domain/kernel clock, but now the driver defaults to the HSE clock, which is
the chip default. Update existing boards to continue to use the PLL1_Q
clock.

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2024-01-10 20:59:55 -05:00
Gerard Marull-Paretas 0f73e8fd3e dts: arm/riscv: gigadevice: s/gigadevice/gd
To stay consistent with other vendors, use vendor prefix (gd).

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-10 20:59:21 -05:00
Gerard Marull-Paretas b3d8fc5e82 soc: arm: gigadevice: s/gigadevice/gd_gd32
Gigadevice was inconsistent with the convention established by other SoC
families, that is, use <vnd_prefix>_<family>. For example, ST STM32 uses
st_stm32. Note that GD32VF103, under soc/riscv, has already been
adjusted.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-10 20:59:21 -05:00
Mateusz Holenko e3deb44bc4 boards: arduino_portenta_h7: enable mailbox
The mailbox peripheral is actively accesses by stm32_hsem functions,
so it should be marked as enabled in DTS.

Signed-off-by: Mateusz Hołenko <mholenko@antmicro.com>
2024-01-10 20:57:24 -05:00
Kapil Bhatt 773ebe9c41 net: wifi_shell: Update scan argument shell
Update the example of scan -c argument.
Default value for max channels is set to 3,
So, update the example according to that.
Add closing bracket in -s.

Signed-off-by: Kapil Bhatt <kapil.bhatt@nordicsemi.no>
2024-01-10 20:56:32 -05:00
Kapil Bhatt 3e8dbaf75f net: wifi_utils: Fix max channels allow for scan
Fix the maximum channels allow for scan command
input.

Signed-off-by: Kapil Bhatt <kapil.bhatt@nordicsemi.no>
2024-01-10 20:56:32 -05:00
Andrzej Kuros c4ce235973 modules: hal_nordic: remove NRF_802154_ENERGY_DETECTED_VERSION
The macro `NRF_802154_ENERGY_DETECTED_VERSION` is no longer required
because transition of nrf 802154 API is done.

Signed-off-by: Andrzej Kuroś <andrzej.kuros@nordicsemi.no>
2024-01-10 20:55:05 -05:00
Andrzej Kuros a15c24ad75 manifest: update hal_nordic revision
This commit updates revision of hal_nordic to bring the latest changes
in the nRF IEEE 802.15.4 driver.

Signed-off-by: Andrzej Kuroś <andrzej.kuros@nordicsemi.no>
2024-01-10 20:55:05 -05:00
Bartosz Bilas e8f223dbe8 drivers: charger: bq24190: fix api and init functions references
There is no need to use & as a function reference, so remove it.

Signed-off-by: Bartosz Bilas <b.bilas@grinn-global.com>
2024-01-10 20:54:04 -05:00
Jeeva Kandasamy 2a4794e98a drivers: pwm: fix esp32-s3 ledc pwm low frequency
ESP32 - S2,S3 and C3 variants have only 14 bits counter.
where as the plain ESP32 variant has 20 bits counter.
application failed to set low frequency(1Hz) in S2, S3 and C3 variants.
to get very low frequencies on these variants,
frequency needs to be tuned with 18 bits clock divider.
so select the slow clock source (1MHz) with highest counter resolution.
this can be handled on the func'pwm_led_esp32_timer_set' with 'prescaler'.

Signed-off-by: Jeeva Kandasamy <jkandasa@gmail.com>
2024-01-10 20:53:07 -05:00
Keith Packard cdc686eecc compiler/gcc: _FORTIFY_SOURCE=1 doesn't mean compile-time only checks
_FORTIFY_SOURCE=1 differs from _FORTIFY_SOURCE=2 only in the bounds
checking mode that it uses.

With _FORTIFY_SOURCE=1, bounds checks are 'loose', allowing access to the
whole underlying object, not just the subset referenced in the expression
(e.g, the bounds of a struct member is the whole struct, not just the
member).

With _FORTIFY_SOURCE=2, bounds checks are strict, meaning that the bounds
of an expression are limited to the referenced value.

Both of these perform their checks at runtime, calling _chk_fail if the
bounds check fails. That's done in the __*_chk functions included in the C
library. These are always called when _FORTIFY_SOURCE > 0, unless the
compiler replaces the call with inline code.

GCC already does all of the compile-time bounds checking for string and mem
functions when not using -ffreestanding, so there's nothing we need to add
for that to work. That means the security_fortify_compile_time property
should be empty.

Signed-off-by: Keith Packard <keithp@keithp.com>
2024-01-10 20:50:51 -05:00
Keith Packard 97f8b8b6ee scripts/footprint: Avoid fpdiff failure when data changes lots
Bounds check the array access in case the input data changes so that the
number of entries in the 'children' array is not the same. The tool output
with this change isn't terribly useful, but at least it doesn't crash.

Signed-off-by: Keith Packard <keithp@keithp.com>
2024-01-10 20:50:51 -05:00